Output latching circuit for static memory devices

Details Output latching circuit for static memory devices Output latching circuit for static memory devices

1997-02-03

1998-02-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365190, 365233, G11C 700

Patent

active

057151989

ABSTRACT:
An output latching circuit for low power static memory devices guarantees glitch-free operation and high performance. The output latching circuit uses first and second latches respectively connected to receive true and complement pulses from the memory array. Third and fourth latches are respectively connected to outputs of the first and second latches. A pull up device is connected to be controlled by an output of the third latch, and a pull down device is connected to be controlled by an output of the fourth latch. The pull up device and the pull down device are connected in series between first and second voltage sources, and an output is connected to a junction of the pull up and pull down devices. An output control receives a clock input and provides a delayed clock output to the third and fourth latches to transfer data latched in the first and second latches to the third and fourth latches, respectively. A tristate input is connected to reset each of the first, second, third and fourth latches to provide a high impedance state at the output. A strobe input may optionally be connected to reset the first and second latches. In this case, the strobe input pulses just prior to new data arrival from the memory array, resetting the first and second latches and causing a momentary high impedance state to occur.

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