Output interfacing device programmable among three states for a

Details Output interfacing device programmable among three states for a Output interfacing device programmable among three states for a

1996-06-10

1998-03-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365226, G11C 1604, G11C 700

Patent

active

057320250

ABSTRACT:
A three-state output interfacing device for a CMOS memory that comprises a stage for selective control of the device, receiving an input signal (I) at the bit frequency and a control signal (e) and making it possible to deliver, on two ports (A) and (B), either complemented signals (I), or distinct logic levels for driving the device into the high-impedance state, a first inverter stage delivering first inverted logic signals, from the ports (A) and (B), on two ports (C) and (D), a second inverter stage delivering second inverted signals from the ports (C) and (D), a stage for reducing the analog difference between the second inverted signals and for switching the output interfacing device into high-impedance state at ports (E) and (F), and an output stage receiving the signals from the ports (E) and (F) after reduction of analog difference and making it possible to fix and balance the current for charging and discharging the output capacitance of the output interfacing device and its high-impedance switching.

REFERENCES:
patent: 4638182 (1987-01-01), McAdams
patent: 4985644 (1991-01-01), Okihara et al.
patent: 5057711 (1991-10-01), Lee et al.
patent: 5067109 (1991-11-01), Kim et al.
patent: 5295098 (1994-03-01), Kohno

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