Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1995-01-20
1997-12-02
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518909, 365194, 307473, G11C 700
Patent
active
056943610
ABSTRACT:
The turn-on time of an output transistor is minimized to suppress the average value of the load current, and the load is electrically charged with an intermediate potential prior to outputting data to suppress the instantaneous value of the load current. The output circuit holds the load in an open state when a predetermined reset signal has a first logic level, and drives the load from a high-potential side power source or a low-potential side power source depending on the logic level of the output data when said predetermined reset signal changes to a second logic level, wherein the timing at which the reset signal changes from the first logic to the second logic is delayed at least until the logic level of the output data has settled. Furthermore, the load is driven at an intermediate potential between the high-potential side power source voltage, and the low-potential side power source voltage and is then driven on the high-potential side power source or the low-potential side power source depending on the logic level of the output data.
REFERENCES:
patent: 4797573 (1989-01-01), Ishimoto
patent: 5043944 (1991-08-01), Nakamura et al.
patent: 5241502 (1993-08-01), Lee et al.
patent: 5305271 (1994-04-01), Watanabe
patent: 5311076 (1994-05-01), Park et al.
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