Output buffer precharge circuit for DRAM

Details Output buffer precharge circuit for DRAM Output buffer precharge circuit for DRAM

1990-02-27

1991-10-15

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, G11C 700

Patent

active

050580663

ABSTRACT:
An output buffer precharge circuit for DRAM (dynamic random access memory) cells includes a latch, control circuits, an output buffer, and a precharge pulse generating section. The circuit further includes a data transition signal genrating section consisting of MOS (metal-oxide semiconductor) transistors, latches connected to the MOS transistors, inverters and NAND gates for receiving the control precharge pulse from the precharge pulse generating section; and a precharge section consisting of MOS transistors, the gates of which receive the outputs of the data transition signal generating section. Noise can be decreased during the transition from the CMOS level to the TTL (transistor-transition-logic) level, and valid data are charged or discharged in advance so that processing speed can be increased.

REFERENCES:
patent: 4604731 (1986-08-01), Konishi
patent: 4716550 (1987-12-01), Flannagan et al.
patent: 4827454 (1989-05-01), Okazaki
patent: 4893276 (1990-01-01), Okuyama
patent: 4922458 (1990-05-01), Watanabe et al.

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