Out of the box vertical transistor for eDRAM on SOI

Details Out of the box vertical transistor for eDRAM on SOI Out of the box vertical transistor for eDRAM on SOI

2006-10-31

2006-10-31

Tran, Long (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000, C257S301000, C257S302000, C257SE27091, C257SE27095

Reexamination Certificate

active

07129130

ABSTRACT:
The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

REFERENCES:
patent: 6426252 (2002-07-01), Radens et al.
patent: 6429477 (2002-08-01), Mandelman et al.
patent: 6875654 (2005-04-01), Wu et al.
patent: 2002/0076880 (2002-06-01), Yamada et al.

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