Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2008-05-06
2010-06-22
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S700000, C438S702000, C438S703000, C438S713000, C438S719000, C257S170000, C257S244000, C257S374000, C257S510000, C257S513000
Reexamination Certificate
active
07741226
ABSTRACT:
A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater. Next, a conductive metal is formed on the conductive metal nucleation layer. After performing the above processing steps, a backside planarization process is performed to convert the at least one aperture into at least one through via that is now optimally filled with a conductive metal.
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Andry Paul S.
Cooney, III Edward C.
Lindgren Peter J.
Ossenkop Dorreen J.
Tsang Cornelia K.
Garcia Joannie A
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Richards N Drew
Scully , Scott, Murphy & Presser, P.C.
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