Operational analysis device of the scan path type having a singl

Details Operational analysis device of the scan path type having a singl Operational analysis device of the scan path type having a singl

1997-06-23

1999-09-07

Tokar, Michael J.

Electronic digital logic circuitry

With test facilitating feature

326 46, 326 97, 327203, 327225, 371 2234, 371 2236, 324 731, H03K 19096, G01R 3128

Patent

active

RE0362921

ABSTRACT:
The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.

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