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Flavio Scarra

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Bank erasable, flash-EPROM memory

Static information storage and retrieval – Read/write circuit – Erase
Patent

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Circuit for detecting a fault state in a clock signal for microp

Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent

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Circuit for the generation of a scanning clock in an operational

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent

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Circuit for the generation of a scanning clock in an operational

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Patent

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FLASH-EPROM with enhanced immunity from soft-programming of refe

Static information storage and retrieval – Floating gate – Particular biasing
Patent

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Profile ID: LFUS-PAI-P-322312

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