On-line testing for decode logic

Details On-line testing for decode logic On-line testing for decode logic

2009-05-20

2011-11-29

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S031000

Reexamination Certificate

active

08069376

ABSTRACT:
Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction to micro-operations and extraction logic to determine first information about numbers of occurrences of fields in the micro-operations. In one embodiment, the processor further comprises verification logic to indicate whether the decoding results of the instruction are accurate based at least on the first information.

REFERENCES:
patent: 6012155 (2000-01-01), Beausang et al.
patent: 6351802 (2002-02-01), Sheaffer
patent: 6519733 (2003-02-01), Har et al.
C. Metra et al., Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic, 13th European Test Symposium, May 25-29, 2008, pp. 171-176, IEEE Computer Society, Washington, DC.

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