On-die termination latency clock control circuit and method...

Details On-die termination latency clock control circuit and method... On-die termination latency clock control circuit and method...

2010-04-05

2011-10-11

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C327S117000, C327S158000

Reexamination Certificate

active

08035412

ABSTRACT:
A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.

REFERENCES:
patent: 2009/0153186 (2009-06-01), Oh et al.
patent: 2010/0231275 (2010-09-01), Kitagawa
patent: 100649975 (2006-11-01), None
patent: 100734087 (2007-06-01), None
patent: 1020080065794 (2008-07-01), None

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