On-chip standalone self-test system and method

Details On-chip standalone self-test system and method On-chip standalone self-test system and method

2006-09-19

2006-09-19

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C370S249000, C375S221000

Reexamination Certificate

active

07111208

ABSTRACT:
A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

REFERENCES:
patent: 3916379 (1975-10-01), Dulaney et al.
patent: 5477531 (1995-12-01), McKee et al.
patent: 5956370 (1999-09-01), Ducaroir et al.
patent: 5995811 (1999-11-01), Watanabe
patent: 6009104 (1999-12-01), Kalkunte
patent: 6028845 (2000-02-01), Serikawa et al.
patent: 6052362 (2000-04-01), Somer
patent: 6069876 (2000-05-01), Lander et al.
patent: 6201829 (2001-03-01), Schneider
patent: 6208621 (2001-03-01), Ducaroir et al.
patent: 6226290 (2001-05-01), Salett et al.
patent: 6340899 (2002-01-01), Green
patent: 6385236 (2002-05-01), Chen
patent: 6385738 (2002-05-01), Lo
patent: 6389092 (2002-05-01), Momtaz
patent: 6424194 (2002-07-01), Hairapetian
patent: 6693881 (2004-02-01), Huysmans et al.
patent: 6775240 (2004-08-01), Zhang et al.
patent: 6954425 (2005-10-01), Chen et al.
patent: 2001/0016929 (2001-08-01), Bonneau et al.
patent: 2001/0043648 (2001-11-01), Ducaroir et al.
patent: 2002/0018535 (2002-02-01), Hairapetian et al.
patent: 2002/0053056 (2002-05-01), Kuegler et al.
patent: 2003/0035473 (2003-02-01), Takinosawa
patent: 2003/0043752 (2003-03-01), Totsuka et al.
patent: 2003/0149921 (2003-08-01), Lau et al.
patent: 2003/0179777 (2003-09-01), Denton et al.
patent: 410013465 (1998-01-01), None
Hunter et al., “WASPNET: A Wavelength Switched Packet Network”, IEEE Communications Magazine, vol. 37, Issue 3, Mar. 1999, pp. 120-129.
Chown et al., “Integrated Transceiver for FDDI”, IEEE Electronics Components Conference, May 1989, pp. 378-383.
Wu et al., “Design and Verification of Differential Transmission Lines”, IEEE Electrical Performance of Electronic Packaging, Oct. 29-31, 2001, pp. 85-88.

Affiliated with

Also associated with

Rating

On-chip standalone self-test system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with On-chip standalone self-test system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip standalone self-test system and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3564832