Offset spacer process for forming N-type transistors

Details Offset spacer process for forming N-type transistors Offset spacer process for forming N-type transistors

2005-06-14

2005-06-14

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S230000, C438S199000, C438S305000

Reexamination Certificate

active

06905923

ABSTRACT:
A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion on strained semiconductor layers. The process can be utilized for SMOS metal oxide semiconductor field effect transistors (MOSFETs). The strained layer can be a strained silicon layer formed above a germanium layer.

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