Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-24
2000-02-08
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
257316, H01L 218238
Patent
active
060227702
ABSTRACT:
Breakdown and latch-up of field effect transistors integrated with non-volatile semiconductor memory cells requiring voltages higher than logic level voltages for write and erase operations is avoided while limiting process complexity and constraints and increasing potential integration density by using thin film transistors for high voltage switching and isolating the thin film transistors from the substrate by forming the thin film transistors on isolation structures extending between or over elements formed at a surface of a substrate or semiconductor layer. Geometry and doping levels of the thin film transistors is thus made independent of geometry and doping levels of the non-volatile semiconductor memory cells and other field effect transistors operating at lower logic-level voltages. In particular, the thickness of a doped semiconductor layer in which an impurity well may be formed can be determined in a manner to optimize performance of transistors operating at logic level voltages rather than the breakdown voltage which must be withstood by transistors used for controlling write and erase operations of the non-volatile memory cells.
REFERENCES:
patent: 4945067 (1990-07-01), Huang
patent: 4984040 (1991-01-01), Yap
patent: 5073723 (1991-12-01), Da Costa
patent: 5267195 (1993-11-01), Kodama
patent: 5274602 (1993-12-01), Glenn
patent: 5291440 (1994-03-01), Koyama
patent: 5315546 (1994-05-01), Ochii
patent: 5321286 (1994-06-01), Koyama et al.
patent: 5338956 (1994-08-01), Nakamura
patent: 5493139 (1996-02-01), Akiyama et al.
patent: 5502673 (1996-03-01), Riggio, Jr.
patent: 5517044 (1996-05-01), Koyama
patent: 5523970 (1996-06-01), Riggio et al.
patent: 5550773 (1996-08-01), Woerlee et al.
patent: 5620906 (1997-04-01), Yamaguchi et al.
patent: 5897346 (1999-04-01), Yamaguchi et al.
SPIE vol. 2881 pp. 194-200 Entitled: Bonding Techniques For Single Crystal TFT AMLCDs, Author(s): Sonja Van Der Groen, Maarten Rosmeulen, Philippe Jansen, Ludo Determ, Kris Baert.
Hook Terence B.
Nakos James S.
Williams Richard Q.
Bowers Charles
International Business Machines - Corporation
Shkurko Eugene I.
Thompson Craig
LandOfFree
NVRAM utilizing high voltage TFT device and method for making th does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with NVRAM utilizing high voltage TFT device and method for making th, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NVRAM utilizing high voltage TFT device and method for making th will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1680552