Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Plasma
Reexamination Certificate
2008-06-24
2010-11-16
Nhu, David (Department: 2895)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Plasma
C438S311000, C438S680000, C438S733000, C438S009000, C257SE21170, C257SE21400, C257SE21320, C257SE21051, C257SE21411, C257SE21182, C257SE21218, C257SE21229, C257SE21227
Reexamination Certificate
active
07833887
ABSTRACT:
A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.
REFERENCES:
patent: 6413802 (2002-07-01), Hu et al.
patent: 6657252 (2003-12-01), Fried et al.
patent: 6768158 (2004-07-01), Lee et al.
patent: 7491630 (2009-02-01), Shroff et al.
patent: 7601592 (2009-10-01), Oh et al.
patent: 2008/0073723 (2008-03-01), Rachmady et al.
Kavalieros Jack
Rachmady Willy
Intel Corporation
Nhu David
Winkle Robert G.
Winkle, PLLC
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