Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-03-08
2001-08-21
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189011, C365S204000, C365S189110
Reexamination Certificate
active
06278636
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memories and more particularly to memories employing electrically erasable and programmable read-only-memory cells (EEPROM cells).
BACKGROUND OF THE INVENTION
There is an increasing demand for semiconductor memories that can be electrically erased and programmed without the need for refreshing data stored in the memory. Also, there is a trend toward enhancing the storage capacity and the density of integration in memory devices. NAND-type flash memory is one example of a nonvolatile semiconductor memory that provides high capacity and integration density without the need for refreshing stored data.
FIG. 1
contains a block diagram of an array of memory cells and conventional page buffers assigned to the array in a NAND-type flash memory. The memory includes a memory cell array
10
, a page buffer circuit
20
and a Y-pass gate circuit
30
(or referred to as “a switch circuit”). The memory cell array
10
is formed of a plurality of strings
12
(a “string” is a cell unit corresponding to one bit of data) arranged in columns. Each string
12
includes a string selection transistor SSTi (i=0, 1, . . . , m), the gate of which is coupled to a string selection line SSL. Each string
12
also includes a ground selection transistor GSTi (i=0, 1, . . . , m), the gate of which is coupled to a ground selection line GSL. Memory cells MCj (j=0, 1, . . . , n) are connected in series between each string selection transistor SSTi and its associated ground selection transistor GSTi. Control gates of the memory cells are coupled to word lines WLj (j=0, 1, . . . , n). The drain of each string selection transistor SSTi is connected to its corresponding bit line Bli (i=0, 1, . . . , m), and the source of each ground selection transistor GSTi is connected to a common source line CSL.
The page buffer circuit
20
includes page buffers
20
_i (i=0, 1, . . . , m) corresponding to the bit lines BLi, respectively. During a read operation, a page buffer senses data from a selected memory cell and then transfers the data to a data bus DB through the Y-pass gate circuit
30
. Hereinafter, even page buffer
20
_
0
, corresponding to bit line BL
0
, is referred to in describing its constructions. Other page buffers
20
_
1
to
20
_m, corresponding to other bit lines BL
1
to BLm, have the same constructions and functions as those of the page buffer
20
_
0
.
The page buffer
20
_
0
includes PMOS transistor M
2
, six NMOS transistors M
1
and M
3
to M
7
, a latch
40
formed of a pair of inverters INV
1
and INV
2
, and tri-state inverter INV
3
. The NMOS transistor M
1
, whose gate is coupled to signal BLSHF, is connected between a sensing node N
1
and a corresponding bit line BL
0
to adjust a voltage level of the bit line BL
0
which is developed while being activated and to prevent the page buffer
20
_
0
from being influenced by a high voltage when the high voltage is applied to BL
0
. The gate and source of the PMOS transistor M
2
, the drain of which is connected to the sensing node N
1
(at the drain of M
1
), are connected to a signal CURMIR and a power supply voltage Vcc, respectively. The PMOS transistor M
2
supplies current to the bit line BL
0
in response to the signal CURMIR.
As seen from
FIG. 2
, the inverter INV
1
of the latch
40
is formed of two PMOS transistors M
12
and M
13
and one NMOS transistor M
14
connected as illustrated in
FIG. 2
, and the inverter INV
2
of the latch
40
is formed of CMOS inverter well known in the art. The PMOS transistor M
12
is controlled by a signal PBset, which from
FIG. 1
will be understood to be inactivated only when the NMOS transistor M
3
is turned on (i.e. only during a discharge period of the read operation when DCB is active (high)). This is to prevent power noise from being generated when the page buffers are reset and the bit lines are discharged.
Referring again to
FIG. 1
, the NMOS transistor M
3
has its source and gate connected to a ground voltage Vss and a signal DCB, respectively, and is connected between the sensing node N
1
and the ground voltage Vss. The transistor M
3
discharges a voltage of the bit line BL
0
and resets the page buffer
20
_
0
output to a ground level. The NMOS transistor M
4
, the gate of which is coupled to a signal SBL, is connected between a node N
2
of latch
40
and the sensing node N
1
. The drain of the transistor M
4
is connected to the Y-pass gate circuit
30
through tri-state inverter INV
3
, the state of which is controlled by signals Osac and nOsac (the complement of Osac). Data in the latch
40
is transferred to the data bus DB through the tri-state inverter INV
3
and the Y-pass gate circuit
30
. Data to be programmed is transferred to the node N
2
of the latch
40
through the NMOS transistor M
7
, the gate of which is coupled to a signal SPB. Node N
3
(a complementary node of N
2
) of latch
40
is connected to Vss through the NMOS transistor M
5
, whose gate is coupled to the sensing node N
1
, and the NMOS transistor M
6
, whose gate is coupled to a signal Olatch. The NMOS transistors M
5
and M
6
thus set the state of data stored in the latch in response to a voltage level on the bit line BL
0
.
According to the conventional page buffer as described above, when data held in the latch
40
is transferred to the data bus DB during read and program operation, the tri-state inverter INV
3
not only drives the data bus DB in response to a voltage level of the node N
2
, but also prevents charges on the node N
2
from being discharged to the data bus DB. However, the data path of the conventional page buffer is divided into an input path formed of the NMOS transistor M
7
and an output path formed of the tri-state inverter INV
3
. And, the tri-state inverter INV
3
is formed by use of multiple MOS transistors and power lines as well known to ones skilled in the art. For this reason, the conventional page buffer has a high component count that renders it difficult to lay out the tri-state inverters in the page buffers
20
_i within a page buffer region of the flash memory device in which higher capacity and integration density are required.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a nonvolatile semiconduct or memory device having improved page buffers.
In order to attain the above objects, according to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device which contains memory cells arranged in rows and columns, page buffers and Y-pass gate circuit. The page buffers are arranged so as to correspond to the columns, with each page buffer holding a datum. The Y-pass gate circuit selects one or more of the bit lines to transfer data held in latches corresponding to the selected bit lines to a data bus. Each latch has adjustable current driving capacity: a first current driving capacity when data is sensed and latched by corresponding page buffers during a read operation, and a second current driving capacity when data is transferred from the corresponding page buffers to the data bus via the switch circuit during the read operation.
In accordance with one embodiment, the latch of each page buffer comprises an inverter having an input terminal coupled to a corresponding sensing node via the first transfer transistor and an output terminal coupled to a latch controller; a first pull-up transistor having a source coupled to a power supply voltage, a gate coupled to a first control signal, and a drain; a second pull-up transistor having a source coupled to the power supply voltage, a gate coupled to a second control signal, and a drain coupled to the drain of the first pull-up transistor; a third pull-up transistor having a source coupled to a common drain of the first and second pull-up transistors, a gate coupled to the input terminal of the inverter, and a drain coupled to the output terminal of the inverter; and a pull-down transistor having a drain coupled to the input terminal of the inverter, a
Marger & Johnson & McCollom, P.C.
Nguyen Viet Q.
Samsung Electronics Co,. Ltd.
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