Nonvolatile semiconductor memory device and manufacturing...

Details Nonvolatile semiconductor memory device and manufacturing... Nonvolatile semiconductor memory device and manufacturing...

2002-09-24

2003-06-24

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000, C438S593000

Reexamination Certificate

active

06583008

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and manufacturing method thereof, and more particularly, to a flash memory device and manufacturing method thereof.
2. Description of the Related Art
Flash memory devices are classified generally as read only memory (ROM), and unlike random access memory (RAM) devices, they have non-volatility in which data stored in a memory cell can be retained when the power supply is removed. Flash memory devices also allow for high integration, so they are widely used in computer memory cards, etc. Unit cells of flash memory devices have basically the same structure as memory cells of other programmable ROM devices such as erasable programmable ROM (EPROM) or electrically erasable programmable ROM (EEPROM). Each unit cell of a flash memory device includes a cell transistor, that is, a tunnel oxide layer, a floating gate electrode, an intergate dielectric layer, and a control gate, which serves as a word line, all of which are sequentially stacked on a channel region.
FIG. 1
is a plan view showing the main portion of a cell array in a conventional flash memory device.
FIG. 2
is a cross sectional view taken along line A-A′ of
FIG. 1
, based on
FIGS. 1 and 2D
disclosed in Japanese Patent Hei 6-188431. Referring to
FIGS. 1 and 2
, a field oxide layer
14
for isolating an active region, in which a device is formed, as well as the devices themselves, is formed on a silicon substrate
10
. Then, a gate oxide layer
12
is interposed to form a floating gate electrode
16
comprised of polysilicon, on top of which a dielectric layer
23
is interposed to form a control gate electrode
24
comprised of polysilicon continuously run in a plurality of memory devices. The dielectric layer
23
is, e.g., an oxide-nitride-oxide (ONO) layer having two oxide layers
18
and
22
sandwiching a nitride layer
20
.
Referring to
FIGS. 1 and 2
, a memory device in the nonvolatile semiconductor memory device is arranged as follows. Active regions (not shown) of the device extend parallel to one another between the adjacent field oxide layers
14
along the longitudinal direction of the FIG.
1
. The gate oxide layer
12
, which is formed sufficiently thin to permit a charge tunneling, is interposed to form floating gate electrodes
16
in each unit cell of the memory device in a direction perpendicular to the active region. The floating gate electrodes
16
are separated from one another on the field oxide layer
14
. The dielectric layer
23
is interposed on the separated floating gate electrode
16
to form the control gate
24
continuously run in a plurality of unit cells in the same direction to the floating gate electrode
16
. The control gate electrode
24
serves as a word line of the memory device, and only two word lines are arranged to cross each field oxide layer
14
in FIG.
1
.
Meanwhile, a bit line (not shown) goes over the active region, both of which are electrically connected through a contact
28
exposing the surface of the active region. A unit cell transistor is formed at the intersecting portion of the control gate electrode
24
, which is a word line, and the active region. Reference numeral
30
denotes a drain region, which is formed in common between adjacent two unit cells, and reference numeral
32
denotes a source region. Reference numeral
26
denotes a separation region which separates the field oxide layers
14
and channel regions, respectively.
As shown in
FIG. 2
, the floating gate electrode
16
in the nonvolatile flash memory device is etched only on the field oxide layer
14
and separated from the adjacent floating gate electrodes
16
in the unit cell. The floating gate electrodes
16
have the same pattern within the memory cell of the nonvolatile memory device and are repetitively formed in each unit cell. The floating gate electrodes
16
are formed in such a way as to provide a sufficient coupling ratio (C/R). The coupling ratio is used for estimating the quantity of charges accumulated or removed after having been transmitted from a channel region of the silicon substrate
10
to these floating gate electrodes
16
via a gate oxide layer
12
by quantum-mechanical tunneling in each unit cell transistor.
FIG. 3
is a graph of illustrating relationship between a space critical dimension (CD) and a coupling ratio between adjacent floating gate electrodes in a conventional flash memory device. A space CD between the adjacent floating gate electrodes represents a distance between adjacent floating gate electrodes to be separated from each other on the field oxide layer. As the space CD is increased, the length of the floating gate is reduced, and accordingly, a coupling ratio is reduced. Conversely, as the space CD is reduced, the length of the floating gate is increased and a coupling ratio is increased. It can be seen from
FIG. 3
that a space CD is inversely proportional to coupling ratio. Therefore, in order to secure a sufficient coupling ratio, a space CD must be maintained below a predetermined value.
FIG. 4
illustrates another problem that may occur if a space CD between the floating gate electrodes is large in the conventional nonvolatile flash memory device. More specifically, during the manufacture of a nonvolatile flash memory device, a gate oxide layer
12
is interposed on a substrate
10
to form a floating gate electrode
16
pattern, and then an intergate dielectric layer
23
is interposed on the entire surface of the substrate
10
to form a control gate electrode (not shown). In this case, in order to remove the ONO dielectric layer
23
formed on the sidewalls of the floating gate electrode
16
, an etching target is increased, to etch and consume the field oxide layer
14
corresponding to about a thickness “H
2
” of the floating gate electrode
16
to a depth “H
3
”, e.g., to a thickness of at least 800 Å.
Thus, as shown in
FIG. 4
, if the space CD “L
3
” between the adjacent floating gate electrodes
16
, which are electrically separated from each other on the field oxide layer
14
, is large, a difference between the space CD “L
3
”, and a length “L
2
” corresponding to a ridge portion of the field oxide layer
14
, the thickness of which is maintained uniform as “H
1
”, is small, so that a margin against misalignment is not sufficiently provided in a photolithography process. For example, if misalignment occurs in a photolithography process for forming the floating gate electrode
16
, a position on the field oxide layer
14
, in which a material for the floating gate electrode
16
is etched, may be located on the edges of the field oxide layer
14
deviating from the ridge portion thereof. In this case, as described in the foregoing, because the field oxide layer
14
is consumed together in etching the ONO dielectric layer
23
, the field oxide layer is almost removed on the edges thereof having a relatively small thickness, which significantly weakens isolation. Reference character “L
1
” in
FIG. 4
denotes a horizontal distance of the field oxide layer
14
.
As described above, in a process of forming a floating gate electrode in a nonvolatile flash memory device, a reduction in a space CD between floating gate electrodes is essentially required, for which the following conventional methods have been used.
FIGS. 5-11
are cross sectional views showing an example for a process of forming the floating gate electrode of the conventional flash memory device. Firstly, referring to
FIG. 5
, a filed oxide layer
14
and a gate oxide layer
12
are provided over a substrate
10
comprised of a semiconductor material such as silicon using a local oxidation of silicon (LOCOS) process which is widely known as an isolation method. After a floating gate electrode material
16
comprised of polysilicon, a first silicon nitride layer
40
, and a first polysilicon layer
42
are sequentially formed on the entire surface of the substrate
10
, a photoresist pattern
44
a
is formed by a usual photoli

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