Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2007-09-21
2009-06-30
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S154000, C365S205000
Reexamination Certificate
active
07554860
ABSTRACT:
An assembly buffer and bitline driver circuit has two inverters cross-coupled to form an assembly buffer. A high-voltage latch is formed from cross-coupled high-voltage inverters. A first low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the first high-voltage inverter and a second low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the other high-voltage inverter. The gate of the first low-voltage n-channel MOS transistor is coupled to one output of one of the inverters forming the assembly buffer latch and the gate of the second low-voltage n-channel MOS transistor is coupled to the output of the other one of the inverters forming the assembly buffer latch. A pre-load circuit is used to prevent data in an unselected circuit from being disturbed.
REFERENCES:
patent: 6046942 (2000-04-01), Hwang et al.
patent: 6137315 (2000-10-01), Zettler
patent: 6369632 (2002-04-01), Barnes
patent: 6707721 (2004-03-01), Singh et al.
patent: 98/58384 (1998-12-01), None
Lee Poongyeub
Liu Ming-Chi
Actel Corporation
Lewis and Roca LLP
Phung Anh
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