Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-27
2002-12-17
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S593000
Reexamination Certificate
active
06495419
ABSTRACT:
FIELD
This invention relates to the field of semiconductor processing. More particularly, the invention relates to forming nonvolatile memory devices within the same process flow as and on the same substrate with logic devices.
BACKGROUND
Many products use nonvolatile memory devices to store digital information while the products are in a power off mode. One benefit of using nonvolatile memory devices is that the digital information stored in the nonvolatile memory device prior to entering a power off mode is not lost during the power off condition. Because of this favorable trait, many products use nonvolatile memory devices in combination with programmable logic devices. In this manner, the digital information stored in the nonvolatile memory devices is used to program or provide other input to the programmable logic devices. Such combinations of nonvolatile memory devices and programmable logic devices are especially useful in handheld consumer products such as cellular telephones and personal data assistants, which tend to be battery powered and thus may not have a continuous source of power, or for which it is desirable to only require a relatively low amount of power. A further benefit of this combination of nonvolatile memory devices and programmable logic devices is that the programming for the programmable logic devices that is retained within the nonvolatile memory devices is upgradeable from time to time, which thus enables the product to be updated with new versions of the software.
When implemented in a product, such as that described above, a discrete, packaged nonvolatile memory chip is typically mounted on a printed circuit board that contains the electrical connections required to connect the nonvolatile memory chip to a discrete, packaged programmable logic chip. Unfortunately, there are several disadvantages associated with this configuration. First, because two separate packaged devices are required, one for the nonvolatile memory device and another for the programmable logic device, an increased amount of surface area is required on the printed circuit board to accommodate the separately packaged devices.
Second, and again because the nonvolatile memory device is in a separate package from the programmable logic device, a longer period of time is required for the programmable logic device to access the digital information stored in the nonvolatile memory device by sending and receiving signals through the electrical connections in the printed circuit board that connects the nonvolatile memory device to the programmable logic device. Third, using multiple packaged devices tends to increase the cost of the product, because of the additional processing required to fabricate the product and because of the additional size required as a result of the separately packaged devices, as suggested above.
What is needed, therefore, is a process for fabricating a monolithic circuit that contains both nonvolatile memory components and programmable logic components on a single monolithic semiconductor substrate.
SUMMARY
The above and other needs are met by an improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.
A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. The top electrode material layer and the capacitive material layer are removed to substantially the level of the upper surface of the protective material layer, thereby leaving the top electrode layer and the capacitive material layer overlying the gate electrodes for the selected portion of the complementary metal oxide semiconductor devices. In this manner, capacitors are formed from the top electrode material layer, the capacitive material layer, and the gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.
The improved process further includes forming nonvolatile memory devices from the selected portion of the complementary metal oxide semiconductor devices, and forming logic devices of the complementary metal oxide semiconductor devices that are not included in the selected portion of the complementary metal oxide semiconductor devices.
By forming nonvolatile memory devices and logic devices on the same monolithic substrate, the invention offers several advantages. The process allows seamless integration of nonvolatile memory within a generic complementary metal oxide semiconductor fabrication process flow in a cost effective manner. The integration of nonvolatile memory and programmable logic on the same monolithic substrate saves space on printed circuit boards by reducing the need for separately packaged nonvolatile memory and programmable logic devices.
Thus, products that use such integrated monolithic circuits are able to be smaller and lighter than products that do not use such integrated monolithic circuits. Further, the monolithic circuits provide true system on a chip solutions for hand held computing device applications, which solutions result in faster memory access time, since the nonvolatile memory is located on the same chip as the programmable logic. Additionally, software stored in the nonvolatile memory is upgradeable with newer programming revisions, which increases the utile life of the products that use such monolithic circuits, thereby reducing the cost of the product as determined over the utile life of the product.
In another aspect, the invention provides a process for manufacturing a complementary metal oxide semiconductor monolithic circuit having a nonvolatile memory device and a logic device, where the logic device includes a first gate electrode, a first source electrode, and a first drain electrode, and where the nonvolatile memory device includes at least a second gate electrode. All of the electrodes of the various devices are covered by a protective material layer.
The process includes exposing the second gate electrode of the nonvolatile memory device by removing a portion of the protective material layer overlying the second gate electrode of the nonvolatile memory device. A capacitive material layer is formed adjacent and overlying the second gate electrode of the nonvolatile memory device, and a top electrode material layer is formed adjacent and overlying the capacitive material layer.
The first source electrode of the logic device and the first drain electrode of the logic device are exposed by removing portions of the protective material layer overlying the first source electrode and first drain electrode of the logic device, and forming electrical connections through the protective material layer, where the electrical connections make electrical connection with the first source electrode of the logic device and the first drain electrode of the logic device. The process further includes forming electrical contacts adjacent and overlying the top electrode material layer and the electrical connections.
In yet another aspect, the invention provides a monolithic circuit having nonvolatile memory devices and logic devices manufactured according to the above described processes.
REFERENCES:
patent: 5612238 (1997-03-01), Sato et al.
patent: 6037625 (2000-03-01), Matsubara et al.
patent: 6133601 (2000-10-01), Watanabe
patent: 6251729 (2001-06-01), Montree et al.
Chatterjee et al., Sub-100nm Gate Length Metal Gate NMOS
Ahmed Shafqat
Banerjee Robindranath
Bhatt Hemanshu D.
Jr. Carl Whitehead
LSI Logic Corporation
Luedeka Neely & Graham PC
Vockrodt Jeff
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