Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-06-11
2001-08-21
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S335000
Reexamination Certificate
active
06277689
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to nonvolatile memories and particularly to electrically erasable nonvolatile memories.
Nonvolatile memory cells are advantageous since they retain recorded information even when the power to the memory is turned off. There are several different types of nonvolatile memories including erasable programmable read only memories (EPROMs), electrically erasable and programmable read only memories (EEPROMs) and flash EEPROM memories. EPROMs are erasable through light exposure but are electrically programmable by channel electron injection onto a floating gate. Conventional EEPROMs have the same programming functionality, but instead of being light erasable they can be erased and programmed by electron tunneling. Thus, information may be stored in these memories, retained when the power is off, and the memories may be erased for reprogramming, as necessary, using appropriate techniques. Flash EEPROMs are block erased, typically giving them better read access times than regular EEPROMs.
Currently, flash memories have gained considerable popularity. For example, flash memories are often utilized to provide on-chip memory for microcontrollers, modems and SMART cards and the like where it is desirable to store codes that may need fast updating.
While flash memories and EEPROMs are closely related, in many instances flash memories are preferred because their smaller cell size means that they can be made more economically. However, flash memories and EEPROMs often have very similar cell attributes.
Nonvolatile memory cells differ in certain respects from the transistors that are generally utilized in electronic components called logic devices, such as microcontrollers, that work with the memory cells. Logic devices are formed of transistors that use a single gate electrode. Nonvolatile memories usually include two gate electrodes, known as the control and floating gate electrodes, situated one over the other. Because of this structural difference, nonvolatile memories and logic devices may be made by different processes. This may contribute to a substantial increase in process complexity and manufacturing cost.
Particularly with an EEPROM, the electrical programming of the cells normally requires substantial potentials to be applied to the cells. These potentials induce electron tunneling from an N+ region onto the floating gate. Additional complexity may arise from the need to provide substantially larger voltages to memory cells than are needed for normal transistor operation.
While the industry has come to accept the need for separate process technologies for logic and nonvolatile memories and while those in the industry have also come to appreciate that significant voltages are needed to program EEPROMs and significant currents to program flash EEPROMs, there would be a substantial demand for a nonvolatile memory which was both electrically erasable and programmable without the need for special process technologies or for relatively higher programming voltages and higher currents.
Furthermore, with the conventional FLASH EEPROMs, the electrical programming of the cells normally requires high current to be applied to the cells. A relatively minute amount of this electron current becomes injected from the drain depletion region onto the floating gate. Therefore, the injection efficiency (e.g., 10
−6
to 10
−9
) is relatively low. The requirement of high current adds additional complexity because of the design of the high current pump operated at low voltage.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, an electrically erasable and programmable read-only memory includes a sensing cell with a floating gate electrode, a channel, a source and a drain. A bipolar transistor is adapted to supply electrons for programming the floating gate electrode by substrate hot electron injection of electrons on to the floating gate electrode through the channel depletion region. The bipolar transistor is arranged such that its collector is also the biased depletion region of the channel of the sensing cell.
In accordance with still another aspect, a nonvolatile memory includes a semiconductor layer of a first conductivity type. A first well of a second conductivity type opposite to the first conductivity type is formed in the semiconductor layer. The first well is an N-well biased to a potential equal to or more positive than Vss. A second well of the first conductivity type is embedded in the first well. The second well is a negatively biased P-well. A memory cell is formed in the second well. The cell includes a floating gate, a source and a drain. The source and drain are of the second conductivity type.
In accordance with yet another aspect of the present invention, a memory cell includes a semiconductor layer having a N-well. A P-well is embedded in the N-well. The sense transistor has a floating gate and a bipolar transistor arranged to inject electrons into the substrate. The injected (pump) electrons can be accelerated by the electric field under the sense transistor channel and get injected onto the floating gate.
In accordance with yet another aspect of the present invention, a method for programming a memory cell includes the step of turning off a select transistor. Carriers are caused to be injected onto the floating gate by substrate hot carrier injection.
In accordance with still another aspect of the present invention, a method for programming a memory cell includes the step of generating substrate electrons using a bipolar transistor. Substrate electrons are accelerated by the electric field under the channel and are injected onto the floating gate of the memory cell. These accelerated electrons are called substrate “hot” electrons.
In accordance with but another aspect of the present invention, a method for forming a memory cell includes the step of forming a floating gate over a channel in a substrate. A diffusion is formed in the substrate spaced from the channel underneath the floating gate and extending under the floating gate. A source and drain are formed for the cell, arranged substantially transversely to the length of the floating gate.
In accordance with another aspect of the present invention, a nonvolatile memory comprises a sense transistor having a floating gate. A coupling capacitor is formed at one end of the floating gate. The coupling capacitor is arranged to control the potential on the floating gate. The floating gate is free of an overlaying control gate electrode. A tunneling capacitor is formed at another end of the floating gate. The tunneling capacitor provides a path for electrons to be removed from the floating gate. It also acts as part of a charge injector for supplying electrons to the channel region under the sense transistor. The tunneling capacitor includes a junction forming the emitter of a lateral bipolar transistor, the biased depletion region of the sense transistor channel under said floating gate acting as the collector of the lateral bipolar transistor.
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Diorio et al., “A Single-Transistor Silicon Synapse”, IEEE Transactions On Electron Devices, vol. 43, No. 11, Nov. 1996 (pp. 1972-1980).
Jr. Carl Whitehead
Programmable Silicon Solutions
Thomas Toniae M.
Trop Pruner & Hu P.C.
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