Static information storage and retrieval – Read/write circuit – Precharge
Patent
1994-06-07
1995-09-26
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Precharge
365204, 3652335, G11C 700
Patent
active
054539552
ABSTRACT:
A non-volatile semiconductor memory device includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. These transistors are controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with an input address so that the read discharging transistors are kept ON to set the non-selected bit lines at the ground potential before and during the data read operation.
REFERENCES:
patent: 4612631 (1986-09-01), Ochii
patent: 4730279 (1988-03-01), Ohtani
patent: 4980861 (1990-12-01), Herdt et al.
4-Mbit NAND-EEPROM, Ryouhei Kirisawa, et al., pp. 997-1000.
4-Mbit NAND-EEPROM with Tight Programmed VT Distribution, Tomoharu Tanaka, et al., pp. 105-106.
Masuoka Fujio
Momodomi Masaki
Nakamura Hiroshi
Sakui Koji
Shirota Riichiro
Kabushiki Kaisha Toshiba
Popek Joseph A.
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