Non-volatile semiconductor memory and method of manufacturing th

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438279, H01L 218247

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active

058245839

ABSTRACT:
The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

REFERENCES:
patent: 4635347 (1987-01-01), Lien et al.
patent: 4962481 (1990-10-01), Choi et al.
patent: 5017980 (1991-05-01), Gill et al.
patent: 5050125 (1991-09-01), Momodomi et al.
patent: 5073513 (1991-12-01), Lee
patent: 5397723 (1995-03-01), Shirota et al.
Y. Itoh, et al., "An Experimental 4Mb CMOS EEPROM with a NAND structured Cell," ISSCC89, 10.4, Feb. 1989, pp. 134-135.
M. Momodomi et al., "New Device Technologies for 5V-Only 4Mb EEPROM with NAND structure Cell," IEDM 88, 17.1, Dec. 1988, pp. 412-415.
R. Shirota et al., "A New Cell for Ultra High Density 5V-Only EEPROMs," VLSI Technology Digest of Technical Papers, May, 1988, pp. 33-34.
R. Stewart et al., "A High Density EPROM Cell and Array", Symposium on VLSI Technology Digest of Technical Papers; May 1986, pp. 89-90.
M. Momodomi et al., "A High Density NAND EEPROM with Block-Page Programming for Microcomputer Applications," May, 1989; CICC89, pp. 10.1.1-10.1.4.

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