Non-volatile memory device with improved erase speed

Details Non-volatile memory device with improved erase speed Non-volatile memory device with improved erase speed

2011-01-04

2011-01-04

Louie, Wai-Sing (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S261000, C438S387000, C438S591000, C257SE21179

Reexamination Certificate

active

07863128

ABSTRACT:
A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a third dielectric layer formed over the second dielectric layer. The third dielectric layer may have a high dielectric constant and may be deposited at a relatively high temperature. A control gate may be formed over the third dielectric layer.

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Co-pending U.S. Appl. No. 11/008,233, filed Dec. 10, 2004; entitled: “Memory Cell Having Enhanced High-K Dielectric”, by Joong Jeon et al., 30 pages.
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Co-pending U.S. Appl. No. 11/086,310, filed Mar. 23, 2005; entitled: “High K Stack for Non-Volatile Memory”, by Wei Zheng et al., 21 pages.
Co-pending U.S. Appl. No. 11/196,434, filed Aug. 4, 2005; entitled: “SONOS Memory Cell Having High-K Dielectric”, by Takashi Whitney Orimoto et al., 27 pages.

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