Non-volatile memory device having self-aligned gate...

Details Non-volatile memory device having self-aligned gate... Non-volatile memory device having self-aligned gate...

2002-07-09

2003-11-04

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S263000

Reexamination Certificate

active

06642107

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a method for manufacturing a non-volatile memory device having a self-aligned gate structure and a non-volatile memory device formed by the same method.
2. Description of the Related Art
Data programming, which is an operation of a non-volatile memory device, is carried out by applying a voltage coupled at a floating gate with a positive voltage applied to a control gate, directing electrons ejected from a substrate to a floating gate through a tunnel dielectric layer (or a tunnel oxide layer) by F-N tunneling or hot carrier injection, and capturing the electrons in the floating gate. Data erase, which is another operation of a non-volatile memory device, is carried out by directing the electrons in the floating gate back to the substrate through F-N tunneling with a negative voltage applied to the control gate.
The operational speed and performance of such a non-volatile memory device is strongly dependent on the ratio of the voltage coupled at the floating gate to the voltage applied to the control gate. As the coupling ratio increases, the operational speed and performance of the non-volatile memory device are improved. The coupling ratio actually represents the ratio of the voltage coupled at the floating gate to the voltage applied through a wordline to the control gate. The coupling ratio may be varied in accordance with various factors. In a case where the electric charge of the floating gate is initialized to 0 by application of ultraviolet rays and parasitic capacitance is supposed to be 0, the coupling ratio V
fg
/N
cg
can be represented by the ratio of the capacitance generated at an oxide
itride/oxide (ONO) layer, which can be used as a dielectric layer between gate layers, to the sum of the capacitance generated at the oxide
itride/oxide (ONO) layer and the capacitance generated at a tunnel oxide layer (C
ONO
/(C
ONO
+C
tunnel oxide
)).
Accordingly, in order to increase the coupling ratio, the C
ONO
/C
ONO
+C
tunnel oxide
ratio must be increased. Various methods for increasing the C
ONO
/C
ONO
+C
tunnel oxide
ratio including a method for increasing C
ONO
have been proposed. Specifically, in order to increase the area of an ONO layer that is used as a dielectric layer between gate layers, the height of the floating gate can be increased. For example, the thickness of the floating gate in a 0.35 &mgr;m-level NAND type product is about 1000 Å. On the other hand, it is suggested that the thickness of the floating gate in a 0.19 &mgr;m-level NAND type product is about 2000 Å.
That is, in order to maintain a predetermined coupling ratio, it is important to maintain at least a predetermined contact area between the dielectric layer between gate layers and the floating gate. However, since the pitch of memory devices continues to decrease, the height of the floating gate must be increased to maintain the predetermined contact area between the dielectric layer and the floating gate.
The increase in the height of the floating gate causes various problems in a self-aligned gate etching process. The increase in the height of the floating gate means an increase in the aspect ratio of the whole gate structure. As the aspect ratio of the gate structure increases, it becomes more difficult to control the critical dimension (CD), and profile defects, such as undercuts caused by an electron shading effect that may occur at a high aspect ratio, occur more frequently.
FIG. 1
is a diagram illustrating an undercut generation model in a self-aligned gate etching process of a non-volatile memory device. Referring to
FIG. 1
, a gate structure includes a tunnel dielectric layer
21
formed in an active region on a semiconductor substrate
10
, a floating gate
30
formed on the tunnel dielectric layer
21
, an interlayer dielectric layer
25
formed on the floating gate
30
, a control gate
40
formed on the interlayer dielectric layer
25
, and a hard mask
50
formed on the control gate
40
. The floating gate
30
may be formed of conductive polysilicon, and the control gate
40
may be formed of a double layer consisting of a conductive polysilicon layer
41
and a tungsten silicide (WSi
x
) layer
45
. The hard mask
50
is used as an etching mask in the gate etching process.
The etching process for forming the gate structure is performed using the hard mask
50
as an etching mask on the tungsten silicide layer
45
, the polysilicon layer
41
, the interlayer dielectric layer
25
that is an ONO layer, and the polysilicon layer of the floating gate
30
. That is, the etching process is self-aligned. However, during the etching process, electrons may accumulate on upper layers, i.e., the control gate
40
and the hard mask
50
. Accordingly, the trajectory of the ions which etch the underlying layers may be varied by the electrons accumulated on the control gate
40
and the hard mask
50
, and the sidewalls of the floating gate
30
may be etched, thereby generating undercuts. The generation of undercuts in an etching process may cause the profile of the gate structure to deteriorate.
The increase in the aspect ratio of the gate structure caused by the increase in the thickness of the floating gate may cause profile defects and may cause the height of an interlayer dielectric (ILD) layer to increase.
FIG. 2
is a cross-sectional view illustrating an interlayer dielectric layer covering a gate structure of a non-volatile memory device. Referring to
FIG. 2
, after forming a gate structure using such a self-aligned gate etching method, an interlayer dielectric layer
60
is formed to cover the gate structure. Before the deposition of the interlayer dielectric layer
60
, the tunnel dielectric layer
21
may be cured. As a result of curing, the exposed sidewalls of the floating gate
30
and the control gate
40
are oxidized, thereby forming a gate sidewall oxide layer
23
.
Since the interlayer dielectric layer
60
is formed to cover the gate structure, the height of the interlayer dielectric layer
60
increases in accordance with the increase in the thickness of the floating gate
30
. The increase in the height of the interlayer dielectric layer
60
may cause a contact hole, formed in a subsequent process, not to open. For example, when forming a contact
70
for a common source line, a contact hole
75
used to form the contact
70
may not open. Accordingly, to prevent this problem, the height of the interlayer dielectric layer
60
must be reduced. However, in the case of employing a conventional self-aligned gate etching method, it is difficult to decrease the height of the interlayer dielectric layer
60
.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is a first object of the present invention to provide a method for manufacturing a non-volatile memory device having a self-aligned gate structure which is capable of improving the profile of the gate structure.
It is a second object of the present invention to provide a method for manufacturing a non-volatile memory device having a self-aligned gate structure which is capable of preventing a defect of unopened contact holes from occurring in a process for forming a contact, by decreasing the height of an interlayer insulating layer for insulating the gate structure.
In accordance with the invention, there is provided a method for manufacturing a non-volatile memory device capable of forming the control gate by an improved damascene process to be naturally self-aligned with the floating gate. This method includes forming a tunnel dielectric layer on a semiconductor substrate, forming first floating gate patterns on the tunnel dielectric layer, forming mold patterns on the first floating gate patterns to selectively expose predetermined portions of the first floating gate patterns, forming floating gates by removing the exposed portions of the first floating gate patterns using the mold patterns as a mask, forming interlayer dielectric layer pa

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