Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-05-13
2009-11-10
Pham, Hoai v (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C257SE21179
Reexamination Certificate
active
07615437
ABSTRACT:
A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components.
REFERENCES:
patent: 6953965 (2005-10-01), Goda et al.
patent: 7344944 (2008-03-01), Park et al.
patent: 2006/0231822 (2006-10-01), Kim
patent: 2004-014783 (2004-01-01), None
patent: 10-2006-0093160 (2006-08-01), None
patent: 10-0614657 (2006-08-01), None
Lee Choong-Ho
Park Kyu-Charn
Sung Suk-Kang
Lee & Morse P.C.
Pham Hoai v
Samsung Electronics Co,. Ltd.
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