Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-09-07
2009-12-22
Menz, Douglas M (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000, C438S591000
Reexamination Certificate
active
07635633
ABSTRACT:
In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.
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patent: 6627498 (2003-09-01), Willer et al.
patent: 7405441 (2008-07-01), Deppe et al.
patent: 7446371 (2008-11-01), Kim
patent: 2005/0239248 (2005-10-01), Lee
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Choi Han-Mei
Kim Sun-Jung
Lee Seung-Hwan
Oh Se-Hoon
Park Ki-Yeon
Harness & Dickey & Pierce P.L.C.
Menz Douglas M
Samsung Electronics Co,. Ltd.
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