Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1999-05-26
2001-05-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S623000, C438S958000
Reexamination Certificate
active
06228780
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of passivation in the fabrication of integrated circuits, and more particularly, to a method of passivation which will both eliminate metal voiding and improve metal electromigration lifetime in the fabrication of integrated circuits.
(2) Description of the Prior Art
The conventional top metal passivation scheme is a sandwich layer comprising silicon oxynitride, spin-on-glass, and a top layer of silicon nitride. However, after the complete thermal cycle, a void may be found in the metal line.
For example,
FIG. 1
illustrates a partially completed integrated circuit device. Top metal lines
20
are shown. Layer
16
on the semiconductor substrate contains all of the semiconductor device structures and lower level metallization, not shown in detail here. First dielectric layer
22
comprises silicon oxynitride having a thickness of about 1500 Angstroms. A spin-on-glass layer or layers
24
fills the gaps between the metal lines. The top dielectric layer
26
comprises silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD) to a thickness of between about 7000 and 10,000 Angstroms. Scanning electron microscope (SEM) pictures show the presence of metal voids
30
when this conventional passivation scheme is used. Jmax is one index of electromigration lifetime. It is desirable to have a Jmax of at least 1.6 mA/&mgr;m. The top metal line Jmax using the conventional process is between about 0.5 and 1.0 mA/&mgr;m. The void
30
has been seen to be larger than half the size of the metal line.
The inventors have discovered that the metal voiding is a stress-induced void caused by thermal shrinkage of the spin-on-glass layer after the complete thermal cycle has been run. It has been discovered that the spin-on-glass shrinks by about 8% which induces metal voiding. It is desired to find a non-shrinkable passivation scheme to eliminate metal voiding and improve electromigration lifetime.
U.S. Patent 5,681,425 to Chen teaches gap filling by a series of deposition and etching cycles using PECVD TEOS (tetraethoxysilane) oxide and a top passivation layer of silicon nitride. U.S. Patent 5,851,603 to Tsai et al discloses a passivation layer comprising oxide
itride/oxide
itride. The oxide could be a high density plasma (HDP) oxide. U.S. Patent 5,759,906 to Lou discloses a multilayer passivation layer including a first PECVD TEOS oxide layer and a spin-on-glass layer wherein the sidewalls of a via through this layer are coated with a HDP fluoro-silicate glass (FSG) layer to prevent poisoned via contamination. U.S. Pat. No. 5,858,869 to Chen discloses a passivation layer comprising an anisotropic plasma oxide, a polymer, and a FSG layer deposited by HDPCVD. None of these patents mention the metal voiding problem.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming a metal passivation layer in the fabrication of an integrated circuit.
Another object of the present invention is to provide an effective and very manufacturable method of forming a non-shrinkable metal passivation layer in the fabrication of an integrated circuit.
Another object of the present invention is to form a non-shrinkable passivation layer over metal lines so that metal voiding is eliminated.
A further object of the invention is to form a non-shrinkable passivation layer over metal lines that will improve the electromigration lifetime of the integrated circuit device.
A still further object is to form a non-shrinkable metal passivation layer using HDP-CVD oxide and PECVD silicon nitride.
Yet another object of the invention is to form a non-shrinkable metal passivation layer using PECVD oxide and PECVD silicon nitride.
Yet another object is to form a non-shrinkable metal passivation layer that will eliminate metal voiding and improve electromigration lifetime of the integrated circuit device.
In accordance with the objects of this invention a new method of forming a non-shrinkable metal passivation layer that will eliminate metal voiding and improve electromigration lifetime of the integrated circuit device is achieved. Semiconductor device structures are provided in and on a semiconductor substrate and covered by an insulating layer. A metal layer is deposited overlying the insulating layer and patterned to form metal lines wherein there is a gap between two of the metal lines. A non-shrinkable passivation layer is formed according to the following steps: a HDP-CVD oxide or PECVD oxide layer is deposited overlying the metal lines wherein the gap is filled by the HDP-CVD oxide or PECVD oxide layer. A silicon nitride layer is deposited by plasma-enhanced chemical vapor deposition overlying the HDP-CVD oxide layer. The fabrication of the integrated circuit device is completed. Completion of fabrication includes thermal processing. Voids are not formed within the metal lines because the non-shrinkable passivation layer does not shrink during the thermal processing.
REFERENCES:
patent: 5681425 (1997-10-01), Chen
patent: 5759906 (1998-06-01), Lou
patent: 5851603 (1998-12-01), Tsai et al.
patent: 5858869 (1999-01-01), Chen et al.
patent: 6069069 (2000-05-01), Chooi et al.
patent: 6110843 (2000-08-01), Chien et al.
patent: 6114186 (2000-09-01), Jeng et al.
Fu Chu-Yun
Hwang Ruey-Lian
Jang Syun-Ming
Kuo So-Wein
Ackerman Stephen B.
Dang Phuc T.
Nelms David
Pike Rosemary L. S.
Saile George O.
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