Nitrogen treatment of polished halogen-doped silicon glass

Details Nitrogen treatment of polished halogen-doped silicon glass Nitrogen treatment of polished halogen-doped silicon glass

1999-06-22

2002-07-02

Derrington, James (Department: 1731)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C117S926000, C117S926000, C117S926000, C438S690000, C438S691000, C438S694000, C438S759000, C438S761000, C438S762000, C438S763000, C438S784000

Reexamination Certificate

active

06413871

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a method and apparatus for fabricating devices with improved dielectric layers.
Integrated circuits continue to evolve, typically becoming more complex. This increasing complexity arises from the desire to include more capability, i.e., higher levels of integration, on the semiconductor chips from which and on which integrated circuits are fabricated. For example, great effort has gone into making the circuit components (transistors, capacitors, etc.) of integrated devices smaller, bringing the components closer together and allowing more components per unit of chip area.
As device feature sizes in integrated circuits get smaller, new concerns arise about the performance of the integrated circuit. These matters may need to be addressed differently in new generation devices. For example, operating speed and power consumption can be affected by the integrated circuit's sensitivity to the dielectric constant of the material used to electrically insulate conductive structures such as metal traces. Various forms of silicon oxide or silicon-oxide-based glass are often used as insulating material in the fabrication of integrated circuits. Silicon oxide has an acceptably low dielectric constant for some applications, but an even lower dielectric constant is desirable for many types of circuits.
Adding fluorine to silicon oxide to produce what is called fluorine-doped silicon glass (“FSG”) can lower the dielectric constant of the insulating material. However, adding fluorine to the silicon oxide, typically done during a chemical-vapor deposition (“CVD”) process, such as a plasma-enhanced CVD (“PECVD”) process, raises new issues with the manufacturing process. For example, “free” (unbound) fluorine can combine with water, including atmospheric water vapor, to form hydrofluoric acid. This hydrofluoric acid may then corrode or otherwise chemically attack some of the materials used in the manufacture of integrated circuits, such as aluminum metal traces. Furthermore, water absorbed by an FSG film typically increases the dielectric constant of the film, which the fluorine was intended to lower in the first place.
Various techniques have been developed to address the problems that free fluorine and hydrofluoric acid can create. One technique has been to form a “cap” of undoped silicon glass (“USG”) over the FSG to seal the FSG from the ambient atmosphere until the integrated circuit can be further processed, overlying the FSG-USG layer with another film. Other techniques, such as surface heating or baking the wafer, have been developed to stabilize FSG films.
The application of new integrated circuit manufacturing methods limits the utility of conventional FSG stabilization techniques in some fabrication processes, however. For example, chemical-mechanical polishing (“CMP”) techniques are currently incorporated in manufacturing processes of various integrated circuit manufacturers. CMP generally removes a selected amount of material from an integrated circuit wafer and planarizes the surface of the wafer. For example, if a layer of insulating material is deposited over a patterned layer of conductive material, such as traces, at least a portion of the topology of the patterned layer often persists on the surface of the deposited layer. A wide variety of planarizing techniques have been developed. Because of the flat, smooth surface produced by CMP processing, however, it is the most appropriate planarizing technique for some applications. CMP generally uses a polishing pad and specialized polishing compound to remove the high spots on the surface of the wafer and to polish the surface to a flat plane. The flat surface provided by CMP is desirable when, among other reasons, a subsequent layer will be deposited and patterned, especially if very small features will be defined in the subsequent layer. However, because CMP typically removes the top portion of the surface of the layer, the process can interfere with the stabilization techniques used on FSG films when the FSG film is polished.
Therefore, an FSG stabilization technique that is compatible with CMP processing is desirable. It is further desirable that any such FSG stabilization technique be compatible with standard integrated circuit materials and performable in an integrated circuit fabrication environment.
SUMMARY OF THE INVENTION
The invention provides a process and apparatus for fabricating an integrated circuit device on a substrate (e.g., a silicon wafer) that allows for FSG layers to be planarized with a CMP processing step and still maintain their stability during subsequent processing steps.
In one embodiment, an FSG film is deposited on the substrate and then chemically-mechanically polished. The polished surface is subsequently nitrided by exposing the polished surface of the FSG film to nitrogen. For example, the substrate is heated to facilitate diffusion of nitrogen into the FSG film while the substrate is exposed to plasma formed primarily from nitrogen gas (N
2
). In a further embodiment, the substrate is heated using plasma that includes a bias RF component to reduce the source plasma power necessary to attain the desirable surface temperature, thus reducing particulate contamination of the surface of the substrate. It is preferable in such a nitriding process to incorporate nitrogen into the FSG film to a depth of at least 5000 Å, or to at least the via depth, as described below.
For a further understanding of the objects and advantages of the present invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5738574 (1998-04-01), Tolles et al.
patent: 5869149 (1999-02-01), Denison et al.
patent: 5908672 (1999-06-01), Ryu et al.
patent: 6008120 (1999-12-01), Lee et al.
patent: 6103601 (2000-08-01), Lee et al.
S. Takeishi et al., “Stabilizing Dielectric Constants of Fluorine-Doped-SiO2Films by N2-Plasma Annealing,”DUMIC Conference—Feb. 21-22, 1995, pp. 257-259 (Feb. 1995).

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