Nitride ready only memory cell with two top oxide layers and...

Details Nitride ready only memory cell with two top oxide layers and... Nitride ready only memory cell with two top oxide layers and...

2002-01-04

2003-01-21

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S265000, C438S593000

Reexamination Certificate

active

06509231

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nitride ready only memory cell (NROM), and particularly to the nitride ready only memory cell with two top oxide layers and the method for manufacturing the same for avoiding the charge to drain out, which is used to increase the reliabilities of Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash memory and embedded Flash, etc.
2. Description of Related Art
Memories are more and more important for current computer products. When the microprocessors of computers are enhanced, the operation amount of the software is also increased. Therefore, the demand of memories increases. To making memory with large capacity, quick speed, high reliability and a lower cost has become an important requirement in the semiconductor industry.
For example, in the manufacturing of nitride ready only memory cell (NORM cell), referring to
FIG. 1
, a semiconductor substrate
10
is provided. A silicon oxide layer
22
, a silicon nitride layer
24
as the material of the floating gate, and a silicon oxide layer
26
are sequentially deposited thereon. These three layers are so called Oxide-Nitride-Oxide structure (briefly called as ONO layer). Next, this ONO layer is defined by photolithographic technology for deriving a plurality of ONO floating gate structures
20
. Then, N+ ions are implanted between the plurality of ONO floating gate structures
20
. After properly thermal diffusion, a buried ion diffusion area
30
is formed. Then, a buried oxide layer
32
is formed above the buried ion diffusion area.
30
.
Next, referring to
FIG. 2
, a polysilicon layer
40
is deposited on the plurality of ONO floating gate structures
20
and the buried oxide layer
32
. A structure of the polysilicon control gate is defined by photolithographic technology for forming a plurality of word lines. Then, as illustrated in
FIG. 2
, a contact surface is formed between the deposited polysilicon layer
40
and the plurality of ONO floating gate structures
20
. This is a contact surface of a common channel so that after programming the NROM memory cells for writing data, part of the charges trapped in the floating gate will flow out through this contact surface, thereby, the data retention is finite so as to effect the reliability of the memory cells.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the present invention is to provide a nitride ready only memory cell with two top oxide layers and the method of manufacturing the same, the top oxide layer cover the surface of the ONO structure so that a protecting layer is formed on the periphery of the silicon nitride layer in the ONO structure, thereby, the silicon nitride layer has no chance to be communicated with the polysilicon layer. Therefore, the problem encountered in the prior art can be overcome completely.
Another object of the present invention is to provide a nitride ready only memory cell with a preferred ability for retaining data.
Another object of the present invention is to provide a nitride ready only memory cell with two top oxide layers and the method of manufacturing the same, wherein electric charges are effectively trapped in the silicon nitride layer of the ONO structure. Therefore, no extra thermal budget is required.
To achieve the object, by high temperature oxidation (HTO), a more oxide layer is deposited on the floating gate of the ONO structure (Oxide-Nitride-Oxide structure) as a protecting layer so as to prevent the charges trapped in the silicon nitride layer of the ONO floating gate from being discharged between a polysilicon layer and a nitride layer so as to increase the reliability of the memory.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.


REFERENCES:
patent: 6261904 (2001-07-01), Pham et al.
patent: 6319775 (2001-11-01), Halliyal et al.
patent: 6348381 (2002-02-01), Jong et al.
patent: 6362052 (2002-03-01), Rangarajan et al.
patent: 6381179 (2002-04-01), Derhacobian et al.
patent: 6399446 (2002-06-01), Rangarajan et al.

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