Narrow isolation oxide process

Details Narrow isolation oxide process Narrow isolation oxide process

1996-12-31

1999-04-20

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438231, 438297, 438305, H01L 218238, H01L 21336

Patent

active

058952373

ABSTRACT:
A high performance CMOS process using grown field oxide for active area isolation takes advantage of process steps used in LDD transistor fabrication to reduce the chip space occupied by the field oxide. Portions of the spacer oxide layer are retained intact over the field oxide during the etching step used to form the oxide spacers on the sides of the polysilicon gates. The retained spacer oxide portions increase the total oxide thickness in the field area to effectively block the ion implantation used to form the heavily doped portions of the source and drain regions. This enables use, in the initial fabrication steps, of a grown field oxide of reduced thickness and advantageously a correspondingly reduced width so as to reduce the chip space allocated to the field oxide.

REFERENCES:
patent: 5298782 (1994-03-01), Sundaresan
patent: 5523250 (1996-06-01), Jeong et al.
Wolf, "Silicon Processing for the VLSI Era vol. 2: Process Integration", Lattice Press, pp. 327-331, 436-438, 1990.

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