Nanowire transistor with surrounding gate

Details Nanowire transistor with surrounding gate Nanowire transistor with surrounding gate

2006-04-04

2008-09-16

Lindsay, Jr., Walter (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S096000, C438S365000, C438S482000, C257SE33004, C257SE31001, C977S700000, C977S762000

Reexamination Certificate

active

07425491

ABSTRACT:
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

REFERENCES:
patent: 4941026 (1990-07-01), Temple
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5909618 (1999-06-01), Forbes et al.
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6104061 (2000-08-01), Forbes et al.
patent: 6104068 (2000-08-01), Forbes
patent: 6150687 (2000-11-01), Noble et al.
patent: 6177299 (2001-01-01), Hsu et al.
patent: 6191448 (2001-02-01), Forbes et al.
patent: 6320222 (2001-11-01), Forbes et al.
patent: 6350635 (2002-02-01), Noble et al.
patent: 6355961 (2002-03-01), Forbes
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6377070 (2002-04-01), Forbes
patent: 6399979 (2002-06-01), Noble et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6413825 (2002-07-01), Forbes
patent: 6414356 (2002-07-01), Forbes et al.
patent: 6424001 (2002-07-01), Forbes et al.
patent: 6448601 (2002-09-01), Forbes et al.
patent: 6492233 (2002-12-01), Forbes et al.
patent: 6496034 (2002-12-01), Forbes et al.
patent: 6504201 (2003-01-01), Noble et al.
patent: 6531727 (2003-03-01), Forbes et al.
patent: 6559491 (2003-05-01), Forbes et al.
patent: 6566682 (2003-05-01), Forbes
patent: 6639268 (2003-10-01), Forbes et al.
patent: 6649476 (2003-11-01), Forbes
patent: 6664806 (2003-12-01), Forbes et al.
patent: 6720216 (2004-04-01), Forbes
patent: 6801056 (2004-10-01), Forbes
patent: 6818937 (2004-11-01), Noble et al.
patent: 6855582 (2005-02-01), Dakshina-Murthy et al.
patent: 6881627 (2005-04-01), Forbes et al.
patent: 6890812 (2005-05-01), Forbes et al.
patent: 6894532 (2005-05-01), Forbes et al.
patent: 6903367 (2005-06-01), Forbes
patent: 6946879 (2005-09-01), Forbes
patent: 6964903 (2005-11-01), Forbes
patent: 2002/0177265 (2002-11-01), Skotnicki
patent: 2003/0008515 (2003-01-01), Chen et al.
patent: 2003/0227072 (2003-12-01), Forbes
patent: 2004/0007721 (2004-01-01), Forbes et al.
patent: 2004/0108545 (2004-06-01), Ando
patent: 2004/0217391 (2004-11-01), Forbes
patent: 2005/0023616 (2005-02-01), Forbes
patent: 2005/0032297 (2005-02-01), Kamins
patent: 2005/0190617 (2005-09-01), Forbes et al.
patent: 2006/0043471 (2006-03-01), Tang et al.
patent: 2006/0046391 (2006-03-01), Tang et al.
patent: 2006/0046424 (2006-03-01), Chance et al.
patent: 2007/0082448 (2007-04-01), Kim et al.
patent: 2007/0228433 (2007-10-01), Forbes
patent: 2007/0228491 (2007-10-01), Forbes
patent: 2007/0231980 (2007-10-01), Forbes
patent: 2007/0231985 (2007-10-01), Forbes
patent: 19943390 (2001-05-01), None
patent: WO-2005079182 (2005-09-01), None
Adler, E., et al., “The Evolution of IBM CMOS DRAM Technology”,IBM Journal of Research&Development, 39(1-2), (Jan.-Mar. 1995),167-188.
Bryllert, Tomas, et al., “Vertical high mobility wrap-gated InAs nanowire transistor”,IEEE Device Research Conference, Santa Barbara, CA,(Jun. 2005),157-158.
Cho, Hyun-Jin, et al., “A Novel Pillar DRAM Cell for 4Gbit and Beyond”,1998 Symposium on VLSI Technology Digest of Technical Papers, Jun. 9-11, 1998,38-39.
Denton, Jack P., et al., “Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate”,IEEE Electron Device Letters, 17(11), (Nov. 1996),509-511.
Doyle, B. S., et al., “High performance fully-depleted tri-gate CMOS transistors”,IEEE Electron Device Letters, vol. 24, No. 4, (Apr. 2003),263-265.
Doyle, B. S., et al., “Tri-Gate fully-depleted CMIS transistors: fabrication, design and layout”,2003 Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan, Jun. 10-12, 2003,133-134.
Forbes, Leonard, “DRAM Arrays, Vertical Transistor Structures, and Methods of Forming Transistor Structures and DRAM Arrays”, U.S. Appl. No. 11/051,119, filed Feb. 3, 2005, 52 pgs.
Forbes, Leonard, “DRAM Tunneling Access Transistor”, U.S. Appl. No. 11/219,085, filed Aug. 29, 2005, 31 pgs.
Forbes, Leonard, “DRAM With Nanofin Transistors”, 48 pgs., filed Apr. 4, 2006.
Forbes, Leonard, “Etched Nanofin Transistors”, 37 pgs., filed Apr. 4, 2006.
Forbes, Leonard, “Grown Nanofin Transistors”, 37 pgs., filed Apr. 6, 2006.
Forbes, Leonard, “Memory Array With Surrounding Gate Access Transistors and Capacitors With Global and Staggered Local Bit Lines”, U.S. Appl. No. 11/128,585, filed May 13, 2005, 42 pgs.
Forbes, Leonard, “Memory Array With Ultra-Thin Etched Pillar Surround Gate Access Transistors and Buried Data/Bit Lines”, U.S. Appl. No. 11/129,502, filed May 13, 2005, 33 pgs.
Forbes, Leonard, “Surround Gate Access Transistors With Grown Ultra-Thin Bodies”, U.S. Appl. No. 11/175,677, filed Jul. 6, 2005, 28 pgs.
Forbes, Leonard, “Tunneling Transistor With Sublithographic Channel”, 63 pgs., filled Apr. 4, 2006.
Forbes, Leonard, “Ultra-Thin Body Vertical Tunneling Transistor”, U.S. Appl. No. 11/215,468, filed Aug. 29, 2005, 27 pgs.
Forbes, Leonard, “Vertical Transistor, Memory Cell, Device, System and Method of Forming Same”, U.S. Appl. No. 11/151,219, filed Jun. 13, 2005, 39 pgs.
Forbes, Leonard, “Vertical Tunneling Nano-Wire Transistor”, U.S. Appl. No. 11/210,374, filed Aug. 24, 2005, 26 pgs.
Huang, Xuejue, et al., “Sub-50 nm P-Channel FinFET”,IEEE Transactions on Electron Devices, vol. 48, No. 5, (May 2001),880-886.
Kalavade, Pranav, et al., “A novel sub-10 nm transistor”,58th DRC. Device Research Conference. Conference Digest, (Jun. 19-21, 2000),71-72.
Kedzierski, Jakub, et al., “Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)”,IEDM Tech. Diq., (2003),315-318.
Kim, Keunwoo, et al., “Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device”,International Symposium on Low Power Electronics and Design, Newport, CA, Aug. 9-11, 2004; http://www.islped.org,(2004),102-107.
Lee, Choonsup, et al., “A Nanochannel Fabrication Technique without Nanolithography”,Nano Letters, vol. 3, No. 10, (2003), 1339-1340.
Miyano, Shinji, et al., “Numerical Analysis of a Cylindrical Thin-Pillar Transistor (CYNTHIA)”,IEEE Transactions on Electron Devices, vol. 39, No. 8, (Aug. 1992),1876-1881.
Nirschl, TH., et al., “The Tunneling Field Effect Transistor (TFET) as an Add-on for Ultra-Low-Voltage Analog and Digital Processes”,IEEE International Electron Devices Meeting,2004; IEDM Technical Digest, (Dec. 13-15, 2004), 195-198.
Rahman, Anisur, et al., “Theory of Ballistic Nanotransistors”,IEEE Transactions on Electron Devices, vol. 50, No. 9, (Sep. 2003),1853-1864.
Samuelson, Lars, “Semiconductor Nanowires as a Novel Electronic Materials Technology for Future Electronic Devices”,IEEE Device Research Conference, Santa Barbara, CA,(Jun. 2005),245.
Samuelson, L., et al., “Semiconductor nanowires for 0D and 1D physics and applications”,Physica E 25, (Jul. 27, 2004),313-318.
Shimomura, K., et al., “A 1-V 46-ns 16-Mb SOI-DRAM with body control technique”,IEEE Journal of Solid-State Circuits, 32(11), (Nov. 1997),1712-1720.
Shimomura, K., et al., “A 1V 46ns 16Mb SOI-DRAM with Body Control Technique”,1997 IEEE Inte

Affiliated with

Also associated with

Rating

Nanowire transistor with surrounding gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nanowire transistor with surrounding gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nanowire transistor with surrounding gate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3978844