Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-07-03
2009-10-27
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000
Reexamination Certificate
active
07608507
ABSTRACT:
A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.
REFERENCES:
patent: 7233522 (2007-06-01), Chen et al.
patent: 2006/0018181 (2006-01-01), Matsunaga et al.
patent: 05-167080 (1993-07-01), None
patent: 11-145431 (1999-05-01), None
patent: 2001-308209 (2001-11-01), None
Hur Sung-Hoi
Lee Ji-Hwon
Harness & Dickey & Pierce P.L.C.
Patton Paul E
Samsung Electronics Co,. Ltd.
Smith Zandra
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