N/PMOS saturation current, HCE, and Vt stability by contact...

Details N/PMOS saturation current, HCE, and Vt stability by contact... N/PMOS saturation current, HCE, and Vt stability by contact...

2008-05-13

2008-05-13

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S229000, C438S508000, C438S508000

Reexamination Certificate

active

07371629

ABSTRACT:
A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NH3flow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NH3and SiH4flow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.

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