Mux scan cell with delay circuit for reducing hold-time...

Details Mux scan cell with delay circuit for reducing hold-time... Mux scan cell with delay circuit for reducing hold-time...

2005-05-17

2005-05-17

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C327S565000, C716S030000

Reexamination Certificate

active

06895540

ABSTRACT:
A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.

REFERENCES:
patent: 5923676 (1999-07-01), Sunter et al.
patent: 6023778 (2000-02-01), Li
patent: 6698006 (2004-02-01), Srinivasan et al.
“Cost-free Scan: A Low-Overhead Scan Path Design” by Lin et al. in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sep. 1998, page(s): 852-861, vol. 17 Issue 9, Inspec Accession No.: 604173.*
“Test-Point Insertion: Scan Paths Through Functional Logic” by Lin et al. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sep. 1998, pp. 838-851, vol. 17 Issue 9, Inspec Accession No.: 6041730.

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