Multiprocessor serialization with early release of processors

Details Multiprocessor serialization with early release of processors Multiprocessor serialization with early release of processors

1998-04-30

2000-06-20

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

712230, 712231, 712 41, G06F 1206

Patent

active

06079013&

ABSTRACT:
A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e. all processors must pause together), and to allow for CPU retry actions on any of the CPUs in the system at any point in the operation.

REFERENCES:
patent: 4646236 (1987-02-01), Crockett et al.
patent: 4809168 (1989-02-01), Hennessy et al.
patent: 4901233 (1990-02-01), Liptay
patent: 5276878 (1994-01-01), Sutton et al.
patent: 5345567 (1994-09-01), Hayden et al.
patent: 5611062 (1997-03-01), Webb et al.
patent: 5621909 (1997-04-01), Webb et al.
patent: 5673391 (1997-09-01), Webb et al.
patent: 5694617 (1997-12-01), Webb et al.
patent: 5713035 (1998-01-01), Farrell et al.
patent: 5761734 (1998-06-01), Pfeffer et al.
patent: 5819078 (1998-10-01), Farrell et al.
"Fast Parellel Processor Notification" IBM Technical Disclosure Bulletin, vol. 31, No. 4, Sep. 1988, pp. 48-52.
"Method For Spin Loop Detection" IBM Technical Disclosure Bulletin, vol. 32, No. 7, Dec. 1989, pp. 78-82.
"Sixteen-Bit Operating System Fast Safe RAM Semaphore Compatibility In An Intel 80386 Paged Environment" IBM Technical Disclosure Bulletin, vol. 34, No. 4A, Sep. 1991, pp. 445-447.
"Efficient ESA/370 Read Channel Programming" IBM Technical Disclosure Bulletin, vol. 35, No. 5, Oct. 1992, pp. 107-115.
"MSIS Handling S/370 Serialization In MSIS Without Delay" IBM Technical Disclosure Bulletin, vol. 36 No. 1, Jan. 1993, pp. 466-469.
"Multisequencing In A Single Instruction Stream Processing Of Parallel Streams" IBM Technical Disclosure Bulletin, vol. 37, No. 1, Jan. 1994, pp. 133-139.
"Serial Message Architecture" IBM Technical Disclosure Bulletin, vol. 38, No. 4, Apr. 1995, pp. 601-603.
"Token-Based Serialization of Instructions in a Multiprocessor System" by H. W. Tast et al., USSN 08/689,762, filed Aug. 13, 1996.

Affiliated with

Also associated with

Rating

Multiprocessor serialization with early release of processors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiprocessor serialization with early release of processors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiprocessor serialization with early release of processors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1864093