Multiple thermal annealing method for a metal oxide semiconducto

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438530, H01L 21336

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active

059813474

ABSTRACT:
A method for forming a metal oxide semiconductor field effect transistor (MOSFET). There is first provided a semiconductor substrate. There is then formed upon the semiconductor substrate a gate dielectric layer. There is then formed upon the gate dielectric layer a gate electrode. There is then implanted into the semiconductor substrate while employing the gate electrode as a mask a pair of unactivated source/drain regions at a pair of opposite edges of the gate electrode, where the gate dielectric layer, the gate electrode and the pair of unactivated source/drain regions form an unactivated metal oxide semiconductor field effect transistor (MOSFET). There is then annealed thermally through a first thermal annealing method the semiconductor substrate to form from the pair of unactivated source/drain regions a pair of activated source/drain regions, where the gate dielectric layer, the gate electrode and the pair of activated source/drain regions form an activated metal oxide semiconductor field effect transistor (MOSFET). Finally, there is then annealed thermally through a subsequent second thermal annealing method the semiconductor substrate to form from the activated metal oxide semiconductor field effect transistor (MOSFET) a hot carrier effect (HCE) resistant activated metal oxide semiconductor field effect transistor (MOSFET).

REFERENCES:
patent: 4151008 (1979-04-01), Kirkpatrick
patent: 5389809 (1995-02-01), Haken et al.
patent: 5413968 (1995-05-01), Inoue et al.
patent: 5491099 (1996-02-01), Hsu
patent: 5510296 (1996-04-01), Yen et al.
patent: 5837572 (1998-11-01), Gardner et al.
patent: 5874344 (1999-02-01), Thompson et al.
patent: 5877050 (1999-03-01), Gardner et al.

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