Multiple power levels for a chip within a multi-chip...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S763000

Reexamination Certificate

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10877687

ABSTRACT:
A semiconductor memory chip is provided for packaging along with a system chip in a single semiconductor package having a plurality of external connectors. The memory chip includes a memory storage array for storing data. A plurality of data buffers is provided for writing or reading data between said memory storage array and the system chip within the single semiconductor package. A first power level may be used for each of the plurality of data buffers. At least one test buffer is directly connected to certain of said plurality of external connectors for supporting testing of said memory chip within the single semiconductor package by external test equipment. A second power level may be used for the test buffer.

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