Multiple-capture DFT system for scan-based integrated circuits

Details Multiple-capture DFT system for scan-based integrated circuits Multiple-capture DFT system for scan-based integrated circuits

2005-10-11

2005-10-11

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

06954887

ABSTRACT:
A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

REFERENCES:
patent: 5349587 (1994-09-01), Nadeau-Dostie et al.
patent: 5680543 (1997-10-01), Bhawmik
patent: 5909451 (1999-06-01), Lach et al.
patent: 5991909 (1999-11-01), Rajski et al.
patent: 6070260 (2000-05-01), Buch et al.
patent: 6085336 (2000-07-01), Swoboda et al.
patent: 6115763 (2000-09-01), Douskey et al.
patent: 6195776 (2001-02-01), Ruiz et al.
patent: 6327684 (2001-12-01), Nadeau-Dostie et al.
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 2003/0097614 (2003-05-01), Rajski et al.
patent: 0 965 850 (1999-12-01), None
patent: WO 02/067001 (2002-08-01), None
U.S. Appl. No. 60/089,620, Hassan et al., filed Jun. 16, 1998.
*G. Hetherington et al, “Logic BIST for Large Industrial Designs: Real Issues and Case Studies”, Proc., IEEE International Test Conference, Paper No. 142, 1999, pp. 358-367.
G. Hetherington et al, “Logic BIST for Large Industrial Designs: Real Issues and Case Studies”, Proc., IEEE International Test Conference, Paper No. 142, 1999, pp. 358-367.

Affiliated with

Also associated with

Rating

Multiple-capture DFT system for scan-based integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple-capture DFT system for scan-based integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple-capture DFT system for scan-based integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3441241