Multi-chip configuration to connect flip-chips to flip-chips

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

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C257S686000

Reexamination Certificate

active

07098542

ABSTRACT:
A semiconductor structure includes a carrier having a cavity formed in a top portion thereof, and a plurality of conductive contacts formed on a top surface of the carrier and positioned around the periphery of the cavity. A number of first coplanar dice are back-side mounted to a top surface of the cavity, and a number of second coplanar dice are flip-chip mounted to the first dice, wherein each of the first dice is electrically connected to two corresponding adjacent second dice to connect the dice in a cascade configuration. For some embodiments, selected dice are flip-chip mounted to the carrier. For other embodiments, selected dice are wire-bond connected to the carrier.

REFERENCES:
patent: 5399898 (1995-03-01), Rostoker
patent: 6150724 (2000-11-01), Wenzel et al.
patent: 6489678 (2002-12-01), Joshi
patent: 6731009 (2004-05-01), Jones et al.
patent: 0 559 366 (1993-09-01), None
XILINX, INC., “The Programmable Logic Databook 1998,” pp 4-9 to 4-36 available from Xilinx, Inc., 2100 Logic Drive, San Jose, California, 95124.

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