Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-03
2002-10-15
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000, C438S289000, C438S302000, C438S527000
Reexamination Certificate
active
06465315
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a transistor and a method of manufacturing it. The transistor includes a local compensation implant.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process vertically introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is vertically doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, and critical dimensions of MOSFETS are reduced, proper design and engineering of channel doping profiles becomes more critical to the operation of small-scale transistors. For example, optimized channel doping profiles can provide excellent immunity to short-channel effects, such as threshold voltage roll-off and drain induced barrier lowering. Immunity to short-channel effects can make devices robust with respect to random process variations (especially gate length variations). For example, in a MOSFET with a uniformly doped channel (without any channel profile engineering), the threshold voltage (V
th
) drops rapidly as gate length (Lg) is reduced.
Generally, the suppression of short-channel effects is related to the lateral non-uniformity of the channel doping profile (e.g., the ratio between the peak concentration of the pocket region and the channel doping concentration). The peak concentration of the pocket region is maximized by utilizing a high dosage of dopants when performing the pocket implant.
One form of channel dopant profile engineering which is widely employed in deep MOSFET fabrication processes utilizes pocket implant regions. However, conventional pocket implant techniques can have significant drawbacks. As stated above, conventional pocket implants can require a high dosage of dopants (dosages of greater than 10
13
dopants per cm squared) to suppress short channel-channel effects. The high dosage associated with the pocket implant can degrade transistor drive current. In addition, when large tilt angle pocket implants are used, the high dosage can cause significant gate depletion effect which also degrades transistor drive current.
The high dosage associated with the pocket implant also can raise the threshold voltage of the transistor. In transistors which use mid-gap metal materials (Tungsten (W), Molybdenum (Mo), and Titanium Nitride (TiN)) as gate conductors, a raised threshold voltage can be problematic. Transistors using mid-gap metals as gate conductors have a larger work function than doped polysilicon. Therefore, pocket implant dosages which are acceptable for polysilicon gate transistors may not be acceptable for mid-gap metal gate transistors because the threshold voltage becomes too large.
Thus, there is a need for a transistor with optimized channel profile engineering without requiring a high dosage pocket implant. Further, there is a need for a method of manufacturing a transistor that is not susceptible to short-channel effects and yet does not utilize a high dosage pocket implant. Further still, there is a need for transistors that have a high ratio between peak dopant concentration in the pocket region and the dopant concentration in the channel region and yet has suitable drive current and threshold voltage characteristics. Even further still, there is a need for a mid-gap metal transistor with channel profile engineering and a method of manufacturing such a transistor.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing a gate structure between a source location and a drain location in a semiconductor substrate. The method also includes providing an angled channel compensation implant in the direction from source location to the drain location, and providing a dual angled pocket implant. The method also includes providing a source/drain extension implant at the source location and the drain location, providing a pair of spacers abutting lateral sides of the gate structure, and providing a deep source/drain implant at the source location and the drain location.
Another exemplary embodiment relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors. The method includes steps of providing at least part of a gate structure on a top surface of a semiconductor substrate, forming a source side channel compensation region with dopants of a first conductivity type, forming a pocket region with dopants of a second conductivity type, and forming source and drain regions with dopants of the first conductivity type. The first conductivity type is opposite the second conductivity type. The gate structure is between the source and drain regions. A channel underneath the gate structure has a lower concentration of dopants of the second conductivity type on a side closer to the source region than on a side closer to the drain region.
Another exemplary embodiment relates to an integrated circuit including a plurality of field effect transistors. Each of the transistors includes a gate structure disposed over a channel, a source side channel compensation region in the channel, a deep source region, a deep drain region, a source extension, a drain extension, a first pocket region, and a second pocket region. The source side channel compensation region is lightly doped with dopants of a first conductivity type. The deep source region and deep drain region are heavily doped with dopants of a second conductivity type. The source extension is integral with the deep drain region, and the drain extension is integral with the deep drain region. The first pocket region is disposed between the channel and the drain extension. The second pocket region is disposed between the source extension and the source side compensation region. The first pocket region and the second region are doped with dopants of the first conductivity type.
REFERENCES:
patent: 4683645 (1987-08-01), Naguib et al.
patent: 5393685 (1995-02-01), Yoo et al.
patent: 5532508 (1996-07-01), Kaneko et al.
patent: 559390
Advanced Micro Devices , Inc.
Brophy Janie J.
Jr. Carl Whitehead
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