MOS transistor with elevated source and drain structures and...

Details MOS transistor with elevated source and drain structures and... MOS transistor with elevated source and drain structures and...

2007-03-21

2009-08-04

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21430

Reexamination Certificate

active

07569456

ABSTRACT:
A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

REFERENCES:
patent: 4513303 (1985-04-01), Abbas et al.
patent: 4998150 (1991-03-01), Rodder et al.
patent: 5021845 (1991-06-01), Hashimoto
patent: 5079180 (1992-01-01), Rodder et al.
patent: 5144393 (1992-09-01), Yamaguchi et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5677214 (1997-10-01), Hsu
patent: 6051473 (2000-04-01), Ishida et al.
patent: 6087235 (2000-07-01), Yu
patent: 6093947 (2000-07-01), Hanafi et al.
patent: 6278164 (2001-08-01), Hieda et al.
patent: 6284606 (2001-09-01), Samudra et al.
patent: 6346447 (2002-02-01), Rodder
patent: 6376318 (2002-04-01), Lee et al.
patent: 6528847 (2003-03-01), Liu
patent: 6544822 (2003-04-01), Kim et al.
patent: 6548875 (2003-04-01), Nishiyama
patent: 6569737 (2003-05-01), Park et al.
patent: 2002/0000635 (2002-01-01), Liu
patent: 2002/0008261 (2002-01-01), Nishiyama
patent: 2002/0037619 (2002-03-01), Sugihara et al.
patent: 2002/0045317 (2002-04-01), Oishi et al.
patent: 2002/0072181 (2002-06-01), Tseng
patent: 2002/0117725 (2002-08-01), Oowaki et al.
patent: 2002/0171107 (2002-11-01), Cheng et al.
patent: 2005/0164433 (2005-07-01), Doris et al.
patent: 10-189966 (1998-07-01), None
patent: 2002-94051 (2002-03-01), None
patent: 2002-100762 (2002-04-01), None
patent: 2002-124665 (2002-04-01), None
patent: 980033205 (1996-07-01), None
patent: 2001-0064118 (2001-07-01), None
patent: 2002-0003625 (2002-01-01), None
patent: 10-0344733 (2002-07-01), None

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