Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-08
2001-11-06
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S596000, C438S595000, C438S267000
Reexamination Certificate
active
06312995
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to ultra-large-scale integration (ULSI) MOSFET integrated circuits. More particularly, it relates to a new and novel MOS transistor and a method of fabricating the same for ULSI systems which includes two assisted-gate electrodes to form ultra-shallow “pseudo” source/drain extensions.
As is generally known, in recent years advances made in the semiconductor process methodologies have dramatically decreased the device dimension sizes and have increased the circuit density on the IC chips. A MOSFET (metal-oxide-semiconductor field-effect transistor) device such as an N-channel MOS transistor or a P-channel MOS transistor has been used extensively for ultra-large-scale integration applications. Typically, the MOSFET devices are fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single crystal semiconductor substrate. The gate electrode is used as a diffusion or implant barrier mask to form self-aligned source/drain regions in the substrate adjacent to and on opposite sides of the gate electrode. The distance from the source region to the drain region under the gate electrode is defined as the “channel length” of the MOSFET device. Currently, the channel length dimension is less than 0.5 microns.
In order to increase the speed of the MOSFET devices, there has existed in the micro-electronics industry over the past two decades an aggressive scaling-down of the channel length dimensions. However, as the channel length reduction of the MOS transistor occurs, the source/drain extension junction depth must also be likewise aggressively reduced down in order to achieve acceptable immunity to the problem of “short-channel effects.” One method of solving this short-channel effect problem is to form ultra-shallow extensions. Unfortunately, this method suffers from the drawback that it is very difficult to form such ultra-shallow extensions by using the conventional ion implantation technique. As a result, the problem of forming ultra-shallow extensions has become one of the major concerns for advanced deep-submicron MOSFET technology which limits its performance.
In view of the foregoing, there exists a need for MOS transistor and a method of fabricating the same for use in ULSI applications so as to provide ultra-shallow extensions without using the ion implantation process.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel method for fabricating a MOS transistor for use in ultra-large-scale integration applications.
It is an object of the present invention to provide an improved MOS transistor structure and a method of fabricating the same for use in ULSI applications.
It is another object of the present invention to provide an improved MOS transistor and a method of fabricating the same for ULSI applications which includes two assisted-gate electrodes to form ultra-shallow “pseudo” source/drain extensions.
It is still another object of the present invention to provide an improved MOS transistor structure which is comprised of a composite gate structure formed of a main gate region and a pair of assisted-gate regions disposed adjacent to and on opposite sides of the main gate region via an oxide layer.
In accordance with a preferred embodiment of the present invention, there is provided a MOS transistor with assisted-gate electrodes for ultra-large-scale integration. A thin gate dielectric layer is formed on a surface of a semiconductor substrate. A composite gate structure is formed over the thin gate dielectric layer. The composite gate structure consists of a main gate region and a pair of assisted-gate regions disposed adjacent to and on opposite sides of the main gate region via an oxide layer. Source/drain regions are formed on the semiconductor substrate on opposite sides of the pair of assisted-gate regions. Sidewall spacers are formed on each side of the pair of assisted-gate regions. Silicide contacts are formed over the source/drain regions and the composite gate structure.
REFERENCES:
patent: 5358879 (1994-10-01), Brady et al.
patent: 5741736 (1998-04-01), Orlowski et al.
King, et al., “Polycrystalline Silicon-Germanium Thin-Film Transistors”, IEEE Transactions on Electron Devices, vol. 41, No. 9 pp. 1581-1591, Sep. 1994.
Advanced Micro Devices , Inc.
Chin Davis
Jr. Carl Whitehead
Novacek Christy
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