MOS transistor structure and method of fabrication

Details MOS transistor structure and method of fabrication MOS transistor structure and method of fabrication

2003-01-07

2004-09-28

Wojciechowicz, Edward (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S183000, C438S199000, C438S300000, C438S301000, C257S288000, C257S408000

Reexamination Certificate

active

06797556

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more specifically to a metal oxide semiconductor transistor.
2. Discussion of Related Art
Today literally millions of individual transistors are coupled together to form very large-scale integrated (VSLI) circuits, such as microprocessors, memories, and application specific integrated circuits (IC's). Presently, the most advanced IC's are made up of approximately three million transistors, such as metal oxide semiconductor (MOS) field effect transistors having gate lengths on the order of 0.25 &mgr;m. In order to continue to increase the complexity and computational power of future integrated circuits, more transistors must be packed into a single IC (i.e., transistor density must increase). Thus, future ultra large-scale integrated (ULSI) circuits will require very short channel transistors with effective gate lengths less than 0.1 &mgr;m. Unfortunately, the structure and method of fabrication of conventional MOS transistors cannot be simply “scaled down” to produce smaller transistors for higher density integration.
The structure of a conventional MOS transistor
100
is shown in FIG.
1
. Transistor
100
comprises a gate electrode
102
, typically polysilicon, formed on a gate dielectric layer
104
, which in turn is formed on a silicon substrate
106
. A pair of source/drain extensions or tip regions
110
are formed in the top surface of substrate
106
in alignment with outside edges of gate electrode
102
. Tip regions
110
are typically formed by well-known ion implantation techniques and extend beneath gate electrode
102
. Formed adjacent to opposite sides of gate electrode
102
and over tip regions
110
are a pair of sidewall spacers
108
. A pair of source/drain contact regions
120
are then formed, by ion implantation, in substrate
106
substantially in alignment with the outside edges of sidewall spacers
108
.
As the gate length of transistor
100
is scaled down in order to fabricate a smaller transistor, the depth at which tip region
110
extends into substrate
106
must also be scaled down (i.e., decreased) in order to improve punch-through characteristics of the fabricated transistor. Unfortunately, present techniques can not scale the size of the tip regions to support the scaling of the gate length.
SUMMARY OF THE INVENTION
An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.


REFERENCES:
patent: 5824587 (1998-10-01), Krivokapic
patent: 5970351 (1999-10-01), Takeuchi
patent: 6057582 (2000-05-01), Choi

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