MOS transistor having a recessed gate electrode and...

Details MOS transistor having a recessed gate electrode and... MOS transistor having a recessed gate electrode and...

2005-06-17

2009-06-23

Richards, N Drew (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S156000, C438S268000, C438S389000

Reexamination Certificate

active

07550352

ABSTRACT:
A MOS transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes an isolation layer formed at a predetermined region of a semiconductor substrate to define an active region and double trench regions formed in the active region. The double trench region is composed of an upper trench region crossing the active region and a lower trench region located under the upper trench region. Thus, the active region is divided into two sub-active regions. Sidewalls of the upper trench region are covered with a spacer, which is used as an etching mask to form the lower trench region in the semiconductor substrate of the upper trench region. The upper and lower trench regions are then filled with a gate electrode. Also, high concentration source/drain regions are formed at the top surfaces of the sub-active regions respectively. Therefore, an effective channel length of the MOS transistor is determined according to the dimension of the lower trench region.

REFERENCES:
patent: 5317346 (1994-05-01), Garcia
patent: 6171916 (2001-01-01), Sugawara et al.
patent: 6358800 (2002-03-01), Tseng
patent: 2003/0068864 (2003-04-01), Il-Yong et al.
patent: 2002-343963 (2002-11-01), None
patent: 1999-0040039 (1999-06-01), None

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