Modular growth of multiple gate oxides

Details Modular growth of multiple gate oxides Modular growth of multiple gate oxides

2002-12-31

2004-11-02

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S275000, C438S981000, C438S787000, C257S391000, C257S392000

Reexamination Certificate

active

06812158

ABSTRACT:

TECHNICAL FIELD
The invention described herein relates generally to semiconductor fabrication, and more particularly to gate oxide fabrication on semiconductor substrates.
BACKGROUND
A gate oxide is a dielectric layer of oxide sandwiched between a transistor's semiconductor channel portion and the gate portion. As the distance between the gate and channel decreases, the transistor's switching speed increases. However, if the gate oxide is too thin for a given channel length at a certain voltage, the electric field across the gate oxide will become excessive and results in leakage or a short. Therefore, different channel lengths require different thicknesses of gate oxides to operate properly at different voltages.
For example, 0.35 &mgr;m CMOS technology uses gate oxide around 60 to 70 Å and power supply of about 3.3V, 0.25 &mgr;m technology uses gate oxide between about 45 to 55 Å and a power supply of about 2.5V, 0.18 &mgr;m technology uses gate oxide around 28 to 34 Å with power supply of about 1.8V, and 0.09 &mgr;m technology is expected to use gate oxide from about 14 to 16 Å and a power supply of about 1V. Each of these technologies represents a generational node, a shift in the relevant standards to a smaller and faster transistor.
However, in each of these generations there is typically a need for system-on-chip (SOC) applications to include CMOS transistors from previous generational nodes. For example, many of the 0.09 &mgr;m node devices also require CMOS transistors designed for intended operation at 1.8V, 2.5V and 3.3 V. Other 0.09 &mgr;m node devices might require only two or three combinations of previous CMOS transistors. Therefore, there is a need for multiple gate oxides on the same chip to enable the combinations of transistors from different technology node.
A commonly used method of growing multiple gate oxides is to perform sequential oxidations and cleans. With each sequential clean and oxidation, a gate oxide can be grown with intended thickness. By repeating the process N times, N number of gate oxides can be grown. Since the oxidation is additive, each oxidation following a previous one will add some thickness to the existing ones. Adjustment of oxidation has to be made to make sure each desired thickness is obtained. Since the oxidation involves temperature and time, the choice of oxide combination requires an oxidation sequence to be developed and tailored for such combination. A different combination of gate oxides requires a different oxidation process sequence and the transistors built on these oxides will be affected because of the different set of thermal cycles seen.
For example, if there were three oxide targets at 16 Å, 28 Å and 64 Å, oxide would need to be grown three times. After the semiconductor substrate is properly prepared (i.e., pre-cleaned), the thickest oxide is grown to about 58 Å at 850° C. with a N
2
anneal. After that oxide is grown, the areas where the thickest and thinnest oxides are desired would be masked. A hydrofluoric acid etch would then be performed on the areas where the medium oxide thickness is desired, removing all oxide from the target areas.
Using a low thermal budget oxidation step, the second oxidation growth could be grown to about 22 Å at 700° C. Although the medium oxide targets would have 22 Å of oxide, the thickest oxide would remain at approximately 58 Å. Another resist masking step would then be performed on only the thin oxide area, masking the thick and medium targets. After removing the oxide in the exposed area, and followed by resist strip, the third and final oxidation growth at 800° C. in NO or oxidation ambient could then be designed to grow 16 Å on the thin target, and additional 6 Å on the medium target and an additional 4 Å on the thick target, making the final oxide growths 16 Å, 28 Å and 64 Å
This series of masks, cleans and oxidations can theoretically achieve any number of oxides on the chip, as long as the additive oxidations are properly calculated. However, the oxides that are grown earlier in the sequence will see several masking and mask removal steps, which potentially causes defects like pinholes and chemical contamination.
Additionally, the above method is not seamlessly modular. Omitting any single oxide affects all other transistors built on the other oxides. The impurities that control device behavior see different thermal cycles and have different concentration profiles depending on the choice of the number of oxides required on the chip. Achieving electrical modularity between common devices formed on a subset of the complete flow would require a combination of dummy thermal cycles (mimicking the omitted oxidation steps) and compensating impurity implants to correct transistor behavior, all of which would lead to a multiplicity of fabrication flows in the manufacturing facility and create the possibility of incorrect processing.
SUMMARY OF THE INVENTION
The present invention provides a technique for growing multiple oxides. In one embodiment, oxides are grown by first implanting a first portion of the semiconductor substrate with a first dose of an oxide growth retardant, implanting a second portion of the semiconductor substrate with a second dose of an oxide growth retardant, and lastly oxidizing the semiconductor substrate in a first environment to grow a first oxide on the first portion and a second oxide on the second portion. Usually, a third portion of the semiconductor substrate is not implanted with any oxide growth retardant so that a third oxide is grown on the third portion during oxidation. The third oxide is the thickest of the three.
The oxidation environment may not be sufficient to grow certain oxides of very thin thicknesses. If this is the case, then a second oxidation may be required. For example, if a thinner oxide were desired, then oxide would be selectively removed through masking and etch process from some part of the third portion of the semiconductor substrate. This would expose an substrate area, allowing the second oxidation to grow a new oxide on that exposed area at a normal unretarded rate. However, since oxidation takes place on the entire semiconductor substrate, a first additional oxide would also be grown on the first portion and a second additional oxide would be grown on the second portion. If there were some remaining part of the third oxide that was not removed, then a third additional oxide would also be grown on that remaining part of the third portion during the second oxidation. After second oxidation, four oxides of different thickness are present on the substrate. Alternatively, a masking step can be applied to selectively expose any of the oxide area. Then a controlled wet etch can be used to thin the exposed oxide to desired thickness. The resist strip and clean will follow. This will create a thinnest fourth oxide without using the second oxidation.
The process is inherently modular. In another embodiment, a first oxidation environment is initially selected. Then, a determination is made as to whether oxides of a first thickness are required on a first portion of the semiconductor substrate. If oxides of the first thickness are required, then the semiconductor substrate is masked so that the first portion is exposed. Then, the exposed first portion is implanted with a first dose of oxide growth retardant, the first dose being appropriate for the first oxidation environment and the first thickness. The mask material is then removed.
After the first determination, another determination is made. Specifically, a determination is made as to whether oxides of a second thickness are required on a second portion of the semiconductor substrate. If oxides of the second thickness are required, then the semiconductor substrate is masked so that the second portion is exposed. Then the exposed second portion is implanted with a second dose of an oxide growth retardant, the second dose being appropriate for the first oxidation envi

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