Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-29
2001-09-11
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S299000, C438S301000, C438S303000, C438S305000, C438S233000, C438S229000
Reexamination Certificate
active
06287953
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits (ICs) or semiconductor chips and a method of fabricating ICs. More specifically, the present invention relates to transistors, such as, field effect transistors, with reduced spacing between gates and local interconnects and a method of fabricating such transistors.
BACKGROUND OF THE INVENTION
Certain integrated circuits (ICs) and IC fabrication processes utilize local interconnects to electrically couple transistor elements. Local interconnects can connect a drain, source, or gate of one transistor to a drain, source, or gate of another transistor. Additionally, local interconnects can connect the drain, source, or gate of one transistor to the drain, source, or gate of the same transistor or to other circuits or conductors within the IC. Generally, conventional local interconnects are formed below a first aluminum (Al) or metal layer associated with an IC (e.g., at the same level or below the top surface of a first thick insulating layer over the semiconductor substrate).
Local interconnects can be created in a trench etch and fill process before the first metal layer is provided over the first thick insulating layer. Local interconnects are generally formed after transistors are formed on the semiconductor substrate and covered by the first thick insulating layer. The thick insulating layer is etched to form trenches which connect the various circuit and transistor elements in accordance with the particular design of the IC. The trenches are filled with a conductive material, such as, polysilicon, tungsten, or other metal to complete the local interconnect. In this way, connection s between transistors, nodes, and other elements can be achieved locally without using the first metal layer.
With the demand for higher levels of integration in semiconductor chips, such as silicon semiconductor chips, and the need for greater density in the circuits on the chips, the spacing between the gates of field effect transistors (FET) when forming local interconnects to the source and drain of the FET becomes more is and more critical. This is especially the case with a microprocessor IC or chip of which a large portion of the real estate of the chip is a static random access memory (SRAM). For increased performance of future microprocessors, the storage capacity of the SRAM must increase, thereby requiring a larger portion of real estate of the microprocessor.
Since the FET is fabricated prior to the formation of the local interconnects, conventional processes include a lithographic mask design which provides for additional space between local interconnect openings and the polysilicon gate to prevent accidental shorting of the source and/or drain to the gate across the local interconnect. This additional space in the layout or mask design wastes valuable real estate of the silicon wafer. Therefore, it would be desirable to create minimum spaced local interconnects without regard to the presence of the gate of the FET in the spaces between the local interconnects.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating an integrated circuit (IC) with minimal spacing between gates of FETs and the local interconnects.
Another object of present invention is to provide an integrated circuit fabrication method in which the local interconnect can be fabricated without regard to the presence of the gates of the FETs in the spaces between the local interconnects.
Yet another object of the present invention is to provide an IC structure, wherein the gate conductor and the insulative spacers (combined) preferably have a width of one lithographic feature.
A further object of the present invention is to provide an integrated circuit fabrication method in which the fabrication of the local interconnects controls the fabrication spacing of the gate.
In accordance with the present invention, an integrated circuit semiconductor substrate is fabricated by first forming the local interconnects to the source and drain of an FET prior to the formation of the gate. The fabrication method comprising the steps of: forming on a semiconductor substrate a thick insulating layer; forming spaced apart openings in the insulating layer for creating a source and drain; filling each of said openings with a conductive material to form local interconnects; removing the portion of the insulating layer between the local interconnects to form an opening; forming a gate oxide on the semiconductor substrate in the opening; and forming a gate electrode on the gate oxide and between the local interconnects. Preferably, an etch protective or stop layer is formed on the semiconductor substrate before forming the thick insulating layer.
Optionally, a P-type local interconnect mask and N-type local interconnect mask are utilized to form the local interconnect openings, thereby eliminating the need for separate P-type and N-type doping masks. In addition, the conductive material for forming the local interconnects can be the origin of impurities for the source and drain or, preferably, the impurities can be implanted by using the insulating layer as mask for self aligning the implantation. Further, an insulating space is created between the local interconnects and the gate. The space between the pair of local interconnects can be as small as one minimum lithographic feature and the local interconnects can each be as small as one minimum lithographic feature in size so the FET is not greater than three minimum lithographic features.
In accordance with the present invention, an integrated circuit includes a transistor. The integrated circuit includes a pair of local interconnects spaced from each other by as little as a minimum lithograph feature and each local interconnect which can be as small as a minimum lithograph feature in size, and a gate disposed in the space between the local interconnects. The gate is separated from the local interconnects by an insulating liner. One dimension of the transistor can be as small as three lithographic features.
In accordance with yet another exemplary embodiment of the present invention, an integrated circuit includes a transistor. The integrated circuit includes a pair of local interconnects and a gate disposed between the local interconnects. The gate is separated from the local interconnects by an insulating liner.
In accordance with yet another exemplary aspect of the present invention, a reduced gate critical dimension can be achieved. Additionally, the method of the present invention can eliminate the need for silicidation or salicidation steps.
REFERENCES:
patent: 5376578 (1994-12-01), Hsu
patent: 5940710 (1999-08-01), Chung et al.
patent: 6087727 (2000-07-01), Tsutsumi
Holst John C.
Horne Stephen C.
Kepler Nicholas J.
Klein Rich K.
Lee Raymond T.
Advanced Micro Devices , Inc.
Bowers Charles
Foley & Lardner
Nguyen Thanh
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