Minimizing transistor size in integrated circuits

Details Minimizing transistor size in integrated circuits Minimizing transistor size in integrated circuits

1998-07-21

2000-11-14

Elms, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438299, 438302, 438306, H01L 21336

Patent

active

061469548

ABSTRACT:
A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.

REFERENCES:
patent: 5641698 (1997-06-01), Lin
patent: 5821146 (1998-10-01), Chang et al.
patent: 5940710 (1999-08-01), Chung et al.

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