Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-09-13
2005-09-13
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06944809
ABSTRACT:
Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
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Krishnamurthy Sridhar
Lai Andrew W.
Lindholm Jeffrey V.
Mansour Teymour M.
Simmons Randy J.
Cartier Lois D.
Ton David
Xilinx , Inc.
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