Methods of manufacturing non-volatile memory devices having...

Details Methods of manufacturing non-volatile memory devices having... Methods of manufacturing non-volatile memory devices having...

2007-05-15

2010-10-26

Purvis, Sue (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21409

Reexamination Certificate

active

07820516

ABSTRACT:
Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.

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Korean Notice of Allowance (dated Dec. 27, 2007) for counterpart Korean Patent Application No. 10-2006-0059608 is provided for the purpose of certification under 37 C.F.R. §§ 1.97(e).
Office Action for corresponding Korean Application No. 10-2006-0059608 dated Jun. 27, 2007.

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