Methods of manufacturing integrated circuit devices having...

Details Methods of manufacturing integrated circuit devices having... Methods of manufacturing integrated circuit devices having...

2002-01-04

2004-02-10

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S303000, C438S696000

Reexamination Certificate

active

06689654

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 200-1845, filed Jan. 6, 2001, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit devices and manufacturing methods therefor and, more particularly, to contact structures that may connect an integrated circuit substrate to an upper conductive layer and methods of forming same.
BACKGROUND OF THE INVENTION
An integrated circuit device may be formed by depositing one or more conductive layers having a predetermined pattern and one or more insulating layers on a substrate. For example, transistors having a gate, a source region, and a drain region may be formed in active regions of the substrate, and the source/drain regions may be electrically connected to an upper conductive layer, such as a bit line or a lower electrode of a capacitor, through a contact structure.
A method of forming a conventional self-aligned contact structure will be described with reference to FIG.
1
. In
FIG. 1
, a gate pattern
16
, which comprises a gate insulating layer
12
, a gate electrode
13
, a capping layer
14
, a pair of spacers
15
, and a source/drain region
11
are formed on a substrate
10
. An interlayer insulating layer
17
is then formed, which covers the gate pattern
16
. Next, the interlayer insulating layer
17
is etched in a self-aligned manner to form a contact hole
18
. The contact hole
18
is filled with a conductive material to form a contact pad
19
, and then an upper conductive layer (not shown) having a predetermined pattern is formed on the contact pad
19
and the interlayer insulating layer
17
to form a self-aligned substrate contact structure. The capping layer
14
and the spacers
15
may protect the gate electrode
13
when the interlayer insulating layer
17
is etched to form the contact hole
18
.
The self-alignment process may enable formation of a contact in increasingly more highly integrated devices, which may use a narrow area for the contact, and may also ensure a sufficient alignment margin for a photolithographic process. As the integration density of integrated circuit devices continues to increase, however, contact resistance may be problematic. As integration density increases, contact resistance generally increases due to the resistance of polycrystalline silicon and the decreased contact area between a contact pad and a source/drain region. The increase in contact resistance may lower the operational speed and/or hinder the integration of an integrated circuit device.
Several techniques have been used to reduce contact resistance, including: 1) the concentration of impurities used in a process for doping polycrystalline silicon may be increased, 2) the contact pad may be formed of metal, and/or 3) the contact area between a contact pad and a source/drain region may be increased. The first and second techniques may result in impurities or metal diffusing into a source/drain region so that the electrical property of a device may be changed. The third technique may involve increasing the area of a contact hole for the purpose of increasing the contact surface area between a contact pad and a source/drain region. This approach, however, may not be compatible with increasing integration density.
FIGS. 2A and 2B
illustrate integrated circuit devices comprising a substrate,
20
, a device isolation layer
21
, a gate insulating layer
23
, a gate electrode
24
, an interlayer insulating layer
25
, and a contact hole
26
. Silicon layers
27
and
27
′ having the same conductivity type as a source/drain region
22
are formed in a particular area exposed by a contact hole
26
belonging to the source/drain region
22
, thereby increasing the contact area between an upper conductive layer
28
and the source/drain region
22
. Unfortunately, the upper conductive layer
28
is in direct contact with the source/drain region
22
at the edge of each of the silicon layers
27
and
27
′. As a result, impurities or metal from the upper conductive layer
28
may diffuse into the source/drain region
22
.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, an integrated circuit device comprises a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.
In other embodiments, the insulating layer extends on to at least a portion of the source region or the drain region.
In still other embodiments, the lower pad layer has a recessed region in an upper surface thereof, opposite the substrate.
In further embodiments, an interlayer insulating layer is disposed on at least a portion of the gate pattern adjacent the conductive layer.
In still further embodiments, the insulating layer comprises silicon nitride (SiN), and the conductive layer comprises impurity doped polycrystalline silicon, titanium nitride (TiN), and/or tungsten (W).
The present invention may also be embodied as methods of manufacturing integrated circuit devices.


REFERENCES:
patent: 5702986 (1997-12-01), Mathews et al.
patent: 5716861 (1998-02-01), Moslehi
patent: 6017823 (2000-01-01), Shishiguchi et al.
patent: 6329225 (2001-12-01), Rodder
patent: 6365451 (2002-04-01), Havemann
patent: 3292739 (1991-12-01), None
patent: 7183486 (1995-07-01), None

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