Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-30
2003-04-01
Sherry, Michael J. (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000
Reexamination Certificate
active
06541343
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to metal-oxide-semiconductor field effect transistors (MOSFETS) and more particularly to transistor structures having partially isolated source/drain junctions, and methods of making same.
2. Background
The trend of integrating more functions on a single substrate while operating at ever higher frequencies has existed in the semiconductor industry for many years. These higher operating frequencies are generally made possible by advances in both semiconductor manufacturing and digital systems design and architecture.
Improvements in semiconductor manufacturing technology that lead to improved operating frequencies are generally related to improvements in the electrical characteristics of circuit elements, such as transistors and capacitors, and the structures used to interconnect the various circuit elements.
More particularly, one way to realize gains in the operating frequency characteristics of integrated circuits includes reducing parasitic capacitance. Parasitic capacitance tends to slow down the operation of integrated circuits because more current is required to charge and discharge the parasitic capacitors and therefore more time is required to drive various circuit nodes to the desired voltage. A significant amount of parasitic capacitance in integrated circuits exists in the junction capacitance associated with field effect transistors typically found on an integrated circuit.
What is needed is a field effect transistor structure having source/drain terminals with reduced junction capacitance. What is further needed is a method of manufacturing such a structure.
SUMMARY OF THE INVENTION
Briefly, a microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type.
In a further aspect of the invention, a process for forming a microelectronic structure having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to form a source/drain terminal.
REFERENCES:
patent: 4475982 (1984-10-01), Lai et al.
patent: 5110408 (1992-05-01), Fujii et al.
patent: 5908313 (1999-06-01), Chau et al.
patent: 6071783 (2000-06-01), Liang et al.
PCT Search Report for Int'l application # PCT/US00/42279, mailed Oct. 12, 2001, 5 pgs.
Chau Robert S.
McFadden Robert S.
Morrow Patrick
Murthy Anand S.
Pert Evan
Sherry Michael J.
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